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AgeCommit message (Expand)AuthorFilesLines
2018-07-09Check that SC yields the load reservationAndrew Waterman1-0/+9
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
2018-06-18Add reproduce line to the end of debug test logsTim Newsome1-0/+2
2018-05-21Merge pull request #141 from riscv/mrhstestTim Newsome2-23/+46
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome2-23/+46
2018-05-15Merge pull request #139 from riscv/debug-tests-more-singleMegan Wachs2-10/+19
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs2-21/+11
2018-05-14Make DownloadTest properly park other harts.Tim Newsome2-5/+9
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-05-11debug: output some more useful info into the post-mortem dataMegan Wachs1-0/+5
2018-04-30[rv64ua/lrsc] Initialize memory read out. (#135)Christopher Celio1-1/+3
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-28Merge pull request #132 from riscv/debug-clear-satpMegan Wachs1-0/+7
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
2018-04-27Merge pull request #125 from riscv/debug-delete-simMegan Wachs1-17/+0
2018-04-27Merge pull request #130 from riscv/trap_entry_align-1Megan Wachs1-0/+1
2018-04-27debug: add missing align directive on trap_entrytrap_entry_align-1Megan Wachs1-0/+1
2018-04-24Fix race when making logs directoryTim Newsome1-1/+5
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
2018-04-16Merge pull request #123 from riscv/gdb_timeoutTim Newsome2-14/+18
2018-04-09Compute gdb command timeout based on ops estimateTim Newsome2-14/+18
2018-04-09Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121)Andrei Tatarnikov1-3/+3
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome4-0/+6
2018-03-27Test debug authentication.Tim Newsome4-3/+19
2018-03-23Print log filename at the end of the log.Tim Newsome1-0/+1
2018-03-21Make misa.C test conform to Hauser proposalAndrew Waterman1-43/+10
2018-03-20Merge pull request #119 from rishikhan/masterPalmer Dabbelt1-2/+8
2018-03-19Update Makefile to allow for RISCV_PREFIX to be set by the configure --targetrishi1-2/+8
2018-03-01Test debugging with/without a program bufferTim Newsome5-5/+10
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome5-0/+29
2018-02-27Add test for clearing misa.C while PC is misaligned (#117)Andrew Waterman1-1/+79
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome3-10/+9
2018-02-07Link scripts shouldn't be executable.Tim Newsome1-0/+0
2018-01-08Deal with gdb reporting pmpcfg0 not existing.Tim Newsome2-3/+16
2018-01-05Add test for multicore failureTim Newsome2-5/+40
2018-01-02Test access exception behavior for illegal addresses (#111)Andrew Waterman2-0/+71
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome6-8/+20
2017-12-21Add all-tests target.Tim Newsome1-1/+3
2017-12-21Merge pull request #110 from riscv/bump_envMegan Wachs1-5/+5
2017-12-21tests: bump env to pick up new names for CSRsMegan Wachs1-5/+5
2017-12-20Remove `set arch riscv:rv%d`Tim Newsome1-1/+0
2017-12-20Verify that F18 does not exist on FPU-less targetsTim Newsome1-17/+20
2017-12-12Display env variables used when invoking OpenOCDTim Newsome2-6/+11
2017-12-01Ensure there are no unnamed registers.Tim Newsome1-0/+2
2017-11-30Merge pull request #109 from riscv/vcssimTim Newsome1-2/+12
2017-11-30Clean up VcsSim init()Tim Newsome1-2/+12
2017-11-27Rename sbadaddr to satpAndrew Waterman5-14/+14
2017-11-26Rv32ud tests (#108)Torbjørn23-0/+318
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