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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 20:59:06 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 20:59:06 -0800 |
| commit | ce471c7f6845e26aa27af1c132458de68ab0bde9 (patch) | |
| tree | 39e717186921b83f11f48646fdefd9e1745fc303 /isa | |
| parent | 8d64e7a32c62d2239007fb6dcc274751c629b7f8 (diff) | |
| download | riscv-tests-ce471c7f6845e26aa27af1c132458de68ab0bde9.zip riscv-tests-ce471c7f6845e26aa27af1c132458de68ab0bde9.tar.gz riscv-tests-ce471c7f6845e26aa27af1c132458de68ab0bde9.tar.bz2 | |
correctly set SR_EA bit for all vector physical supervisor tests
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64sv/illegal_cfg_nfpr.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_cfg_nxpr.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_inst.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_tvec_regid.S | 2 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_vt_inst.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/illegal_vt_regid.S | 2 | ||||
| -rw-r--r-- | isa/rv64sv/ma_utld.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/ma_utsd.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vld.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vsd.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/ma_vt_inst.S | 1 | ||||
| -rw-r--r-- | isa/rv64sv/privileged_inst.S | 1 |
12 files changed, 14 insertions, 0 deletions
diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S index b271268..2440cbb 100644 --- a/isa/rv64sv/illegal_cfg_nfpr.S +++ b/isa/rv64sv/illegal_cfg_nfpr.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S index 8dac90d..c61d4d9 100644 --- a/isa/rv64sv/illegal_cfg_nxpr.S +++ b/isa/rv64sv/illegal_cfg_nxpr.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S index cddae29..ff8cee1 100644 --- a/isa/rv64sv/illegal_inst.S +++ b/isa/rv64sv/illegal_inst.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S index d57aeca..4cfa1e0 100644 --- a/isa/rv64sv/illegal_tvec_regid.S +++ b/isa/rv64sv/illegal_tvec_regid.S @@ -11,6 +11,8 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator + mfpcr a3,status li a4,(1 << IRQ_COP) slli a4,a4,SR_IM_SHIFT diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S index de026f4..9bb586b 100644 --- a/isa/rv64sv/illegal_vt_inst.S +++ b/isa/rv64sv/illegal_vt_inst.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S index e612a86..120facc 100644 --- a/isa/rv64sv/illegal_vt_regid.S +++ b/isa/rv64sv/illegal_vt_regid.S @@ -11,6 +11,8 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator + mfpcr a3,status li a4,(1 << IRQ_COP) slli a4,a4,SR_IM_SHIFT diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S index 2cc42bc..aff6e1a 100644 --- a/isa/rv64sv/ma_utld.S +++ b/isa/rv64sv/ma_utld.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S index ead6c2c..20249e3 100644 --- a/isa/rv64sv/ma_utsd.S +++ b/isa/rv64sv/ma_utsd.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S index 3ea11e9..b353c43 100644 --- a/isa/rv64sv/ma_vld.S +++ b/isa/rv64sv/ma_vld.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S index fbbc0cd..227955c 100644 --- a/isa/rv64sv/ma_vsd.S +++ b/isa/rv64sv/ma_vsd.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S index d76f26c..85667e4 100644 --- a/isa/rv64sv/ma_vt_inst.S +++ b/isa/rv64sv/ma_vt_inst.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S index 3f04f60..64a7508 100644 --- a/isa/rv64sv/privileged_inst.S +++ b/isa/rv64sv/privileged_inst.S @@ -11,6 +11,7 @@ RVTEST_RV64S RVTEST_CODE_BEGIN + setpcr status, SR_EA # enable accelerator setpcr status, SR_EI # enable interrupt la a3,handler |