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2025-11-16Clear mcountinhibit.ir in minstret test to ensure minstret increments. (#634)Luke Wren1-0/+9
2025-10-30Improve Ziccid test to handle in-order fetch ruleAndrew Waterman1-5/+61
2025-10-24Fix duplicate mulh test case in rv32m tests (#630)404allen4041-1/+1
2025-10-14Merge pull request #629 from aman4150/masterAman2-0/+4
2025-06-13Add Ziccid testAndrew Waterman3-2/+61
2025-06-10apply nInffChih-Min Chao4-4/+4
2025-06-10apply InffChih-Min Chao5-5/+5
2025-06-10apply nInfdChih-Min Chao3-3/+3
2025-06-10apply InfdChih-Min Chao4-4/+4
2025-06-10apply nInfhChih-Min Chao1-1/+1
2025-06-10apply InfhChih-Min Chao2-2/+2
2025-06-10apply sNaNhChih-Min Chao2-2/+2
2025-06-10apply qNaNfChih-Min Chao4-9/+9
2025-06-10apply qNaNdChih-Min Chao4-5/+5
2025-06-10apply sNaNdChih-Min Chao3-5/+5
2025-06-10apply sNaNfChih-Min Chao3-5/+5
2025-06-10macro: define [sq]NaN[dfh] and [n]Inf[dfh]Chih-Min Chao1-0/+18
2025-04-18Fix rv32ud-p-fcvt_w and -recoding being redundant with rv32ufAndrew Waterman3-3/+7
2025-04-15Remove use of qNaN/sNaN in a different way to fix LLVM build (#613)Andrew Waterman9-69/+87
2025-04-15Fix rv64ua-amomaxu_w and rv64ua-amominu_w testcases for rv32 (#611)etterli2-0/+8
2025-04-14Remove use of qNaN/sNaN to fix LLVM build (#612)Andrew Waterman9-22/+35
2025-04-10Add test for pmpaddr[G-1] edge cases (#609)Tim Hutt4-0/+164
2025-04-07Add instret_overflow testAndrew Waterman4-0/+52
2025-04-03Removed irrelevant test (#605)Kathlene Magnus2-71/+0
2025-02-07Added instructions to handle Rs1 and Rd dependency in load-store bypass seque...splinedrive1-0/+14
2025-01-29Add Load-Store and Store-Load Bypass Tests for Forwarding in Pipelined CPU (#...splinedrive7-5/+301
2024-11-16Fix the typo in the Makefrag for the reference to 2-stage-translation.S (#596)Kun Lu1-1/+1
2024-11-11Add hypervisor 2-stage translation test (#558)heiyuen19993-1/+147
2024-08-14Fit riscv-tests to newest riscv spec: renaming sptbr,sbadaddr,mbadaddr (#578)HUJIYONG5-12/+12
2024-05-30Support more basic testing of Zca instructionsAndrew Waterman1-13/+13
2024-05-30Support basic testing of more Zca instructionsAndrew Waterman1-76/+76
2024-03-19ma_addr: permit access faults in lieu of misaligned exceptionsAndrew Waterman1-1/+6
2024-02-18Fix breakpoint testAndrew Waterman1-0/+3
2024-02-19Add zbs test casesRoger Chang19-2/+773
2024-02-19Add zbc test casesRoger Chang9-2/+520
2024-02-19Add zbb test casesRoger Chang45-2/+2665
2024-02-19Add zba test casesRoger Chang14-2/+958
2024-02-03If Svnapot is not implemented, skip the test.Eiji Yoshiya1-0/+11
2024-01-29Uses appropriate addi instruction in lrsc test.Lucas Clemente Vella1-1/+1
2023-04-06Augment LR/SC test to test that SC-after-failed-SC failsAndrew Waterman1-2/+5
2023-04-06Merge pull request #466 from riscv-software-src/spike-zicntrAndrew Waterman1-2/+2
2023-04-06Merge pull request #464 from nervosnetwork/amocmp_wAndrew Waterman4-1/+40
2023-04-06Include Zicntr in Spike ISA stringAndrew Waterman1-2/+2
2023-04-06Add more tests for amomax/maxu/min/minu_wmohanson4-1/+40
2023-03-16Fix breakpoint.S failing when tcontrol is implemented (#463)Luke Wren1-0/+10
2023-02-27rv32ui test misaligned load/store data (#459)Jesse Taube3-5/+9
2023-02-13Fix ma_fetch test for norvc (#454)Yujia Qiao1-1/+1
2023-01-19Fix ma_fetch test for writable misa.C (#449)Jerry Zhao1-3/+3
2023-01-19Pass --misaligned flag to Spike to run ISA tests (#445)Andrew Waterman1-2/+2
2022-12-28Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32Jerry Zhao1-9/+31
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