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authorAndrew Waterman <waterman@cs.berkeley.edu>2016-03-10 14:47:44 -0800
committerAndrew Waterman <waterman@cs.berkeley.edu>2016-03-10 14:48:38 -0800
commit057b1432679ded5dce4149797fa624205baee62e (patch)
tree1b2787116f4e5c9633d1508301edfbdd674213e7 /isa
parent31f39a39dffbdb810b18721bece5c233b91577eb (diff)
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Add missing rv32mi/rv32si tests
Diffstat (limited to 'isa')
-rw-r--r--isa/rv32mi/Makefrag3
-rw-r--r--isa/rv32mi/dirty.S10
-rw-r--r--isa/rv32mi/mcsr.S7
-rw-r--r--isa/rv32mi/wfi.S8
-rw-r--r--isa/rv32si/Makefrag1
-rw-r--r--isa/rv32si/wfi.S7
-rw-r--r--isa/rv64mi/dirty.S4
-rw-r--r--isa/rv64mi/mcsr.S6
8 files changed, 43 insertions, 3 deletions
diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
index 3a5b376..66a0e39 100644
--- a/isa/rv32mi/Makefrag
+++ b/isa/rv32mi/Makefrag
@@ -4,13 +4,16 @@
rv32mi_sc_tests = \
csr \
+ dirty \
illegal \
ma_fetch \
ma_addr \
+ mcsr \
scall \
sbreak \
shamt \
timer \
+ wfi \
rv32mi_mc_tests = \
ipi \
diff --git a/isa/rv32mi/dirty.S b/isa/rv32mi/dirty.S
new file mode 100644
index 0000000..c1f9d19
--- /dev/null
+++ b/isa/rv32mi/dirty.S
@@ -0,0 +1,10 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#undef VM_SV39
+#define VM_SV39 VM_SV32
+
+#include "../rv64mi/dirty.S"
diff --git a/isa/rv32mi/mcsr.S b/isa/rv32mi/mcsr.S
new file mode 100644
index 0000000..0d5a5cd
--- /dev/null
+++ b/isa/rv32mi/mcsr.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#include "../rv64mi/mcsr.S"
diff --git a/isa/rv32mi/wfi.S b/isa/rv32mi/wfi.S
new file mode 100644
index 0000000..d5cb3cb
--- /dev/null
+++ b/isa/rv32mi/wfi.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/wfi.S"
diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index dea3ecf..a40953e 100644
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -7,6 +7,7 @@ rv32si_sc_tests = \
ma_fetch \
scall \
sbreak \
+ wfi \
rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
diff --git a/isa/rv32si/wfi.S b/isa/rv32si/wfi.S
new file mode 100644
index 0000000..8bc9279
--- /dev/null
+++ b/isa/rv32si/wfi.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/wfi.S"
diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 731d80d..73d6c6c 100644
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
# Try a faulting store to make sure dirty bit is not set
li TESTNUM, 2
li t0, 1
- sd t0, dummy, t1
+ sw t0, dummy, t1
# Load new page table
li TESTNUM, 3
@@ -38,7 +38,7 @@ RVTEST_CODE_BEGIN
sfence.vm
# Try a non-faulting store to make sure dirty bit is set
- sd t0, dummy, t1
+ sw t0, dummy, t1
# Make sure R and D bits are set
lw t0, page_table_2
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index 8a451ca..2eeb14c 100644
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -13,8 +13,12 @@
RVTEST_RV64M
RVTEST_CODE_BEGIN
- # Check that mcpuid reports RV64
+ # Check that mcpuid reports the correct XLEN
+#ifdef __riscv64
TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
+#else
+ TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30)
+#endif
# Check that mhartid reports 0
TEST_CASE(3, a0, 0x0, csrr a0, mhartid)