diff options
author | Colin Schmidt <colins@eecs.berkeley.edu> | 2016-02-29 10:00:15 -0800 |
---|---|---|
committer | Colin Schmidt <colins@eecs.berkeley.edu> | 2016-02-29 10:54:27 -0800 |
commit | af7bcec998b72b2b91180c83b45151201fa1c150 (patch) | |
tree | e632d433c598b38499df4e299b893800ad00e428 /isa/rv64ua | |
parent | 9e63c8544ea2e0aea6778defb7b535dbb87b7205 (diff) | |
download | riscv-tests-travis-dev.zip riscv-tests-travis-dev.tar.gz riscv-tests-travis-dev.tar.bz2 |
Separate M, and A from I. Allow disabling of M,A,Ftravis-dev
This allows riscv-tests to be built with a compiler
that supports not just RVG.
Diffstat (limited to 'isa/rv64ua')
-rw-r--r-- | isa/rv64ua/Makefrag | 17 | ||||
-rw-r--r-- | isa/rv64ua/amoadd_d.S | 64 | ||||
-rw-r--r-- | isa/rv64ua/amoadd_w.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amoand_d.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amoand_w.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amomax_d.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amomax_w.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amomaxu_d.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amomaxu_w.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amomin_d.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amomin_w.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amominu_d.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amominu_w.S | 49 | ||||
-rw-r--r-- | isa/rv64ua/amoor_d.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amoor_w.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amoswap_d.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amoswap_w.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amoxor_d.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/amoxor_w.S | 65 | ||||
-rw-r--r-- | isa/rv64ua/lrsc.S | 83 |
20 files changed, 1141 insertions, 0 deletions
diff --git a/isa/rv64ua/Makefrag b/isa/rv64ua/Makefrag new file mode 100644 index 0000000..7acf644 --- /dev/null +++ b/isa/rv64ua/Makefrag @@ -0,0 +1,17 @@ +#======================================================================= +# Makefrag for rv64ua tests +#----------------------------------------------------------------------- + +rv64ua_sc_tests = \ + amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + +rv64ua_mc_tests = \ + lrsc + +rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) +rv64ua_pt_tests = $(addprefix rv64ua-pt-, $(rv64ua_sc_tests)) +rv64ua_pm_tests = $(addprefix rv64ua-pm-, $(rv64ua_mc_tests)) +rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) + +spike_tests += $(rv64ua_p_tests) $(rv64ua_pm_tests) $(rv64ua_pt_tests) $(rv64ua_v_tests) diff --git a/isa/rv64ua/amoadd_d.S b/isa/rv64ua/amoadd_d.S new file mode 100644 index 0000000..c356bed --- /dev/null +++ b/isa/rv64ua/amoadd_d.S @@ -0,0 +1,64 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_d.S +#----------------------------------------------------------------------------- +# +# Test amoadd.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff7ffff800, \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoadd_w.S b/isa/rv64ua/amoadd_w.S new file mode 100644 index 0000000..b3d1953 --- /dev/null +++ b/isa/rv64ua/amoadd_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xffffffff80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoand_d.S b/isa/rv64ua/amoand_d.S new file mode 100644 index 0000000..13019ae --- /dev/null +++ b/isa/rv64ua/amoand_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand_d.S +#----------------------------------------------------------------------------- +# +# Test amoand.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoand_w.S b/isa/rv64ua/amoand_w.S new file mode 100644 index 0000000..a843888 --- /dev/null +++ b/isa/rv64ua/amoand_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomax_d.S b/isa/rv64ua/amomax_d.S new file mode 100644 index 0000000..ea7e2d3 --- /dev/null +++ b/isa/rv64ua/amomax_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sd x0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomax_w.S b/isa/rv64ua/amomax_w.S new file mode 100644 index 0000000..b3adbf0 --- /dev/null +++ b/isa/rv64ua/amomax_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomaxu_d.S b/isa/rv64ua/amomaxu_d.S new file mode 100644 index 0000000..b340873 --- /dev/null +++ b/isa/rv64ua/amomaxu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomaxu_w.S b/isa/rv64ua/amomaxu_w.S new file mode 100644 index 0000000..41346d1 --- /dev/null +++ b/isa/rv64ua/amomaxu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomin_d.S b/isa/rv64ua/amomin_d.S new file mode 100644 index 0000000..e6febbb --- /dev/null +++ b/isa/rv64ua/amomin_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomin_w.S b/isa/rv64ua/amomin_w.S new file mode 100644 index 0000000..96b547b --- /dev/null +++ b/isa/rv64ua/amomin_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amominu_d.S b/isa/rv64ua/amominu_d.S new file mode 100644 index 0000000..a1013f3 --- /dev/null +++ b/isa/rv64ua/amominu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amominu_w.S b/isa/rv64ua/amominu_w.S new file mode 100644 index 0000000..0a9e265 --- /dev/null +++ b/isa/rv64ua/amominu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoor_d.S b/isa/rv64ua/amoor_d.S new file mode 100644 index 0000000..507e877 --- /dev/null +++ b/isa/rv64ua/amoor_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor_d.S +#----------------------------------------------------------------------------- +# +# Test amoor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoor_w.S b/isa/rv64ua/amoor_w.S new file mode 100644 index 0000000..47978ba --- /dev/null +++ b/isa/rv64ua/amoor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoswap_d.S b/isa/rv64ua/amoswap_d.S new file mode 100644 index 0000000..628f537 --- /dev/null +++ b/isa/rv64ua/amoswap_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap.d.S +#----------------------------------------------------------------------------- +# +# Test amoswap.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoswap_w.S b/isa/rv64ua/amoswap_w.S new file mode 100644 index 0000000..c09b866 --- /dev/null +++ b/isa/rv64ua/amoswap_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoxor_d.S b/isa/rv64ua/amoxor_d.S new file mode 100644 index 0000000..f446121 --- /dev/null +++ b/isa/rv64ua/amoxor_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_d.S +#----------------------------------------------------------------------------- +# +# Test amoxor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoxor_w.S b/isa/rv64ua/amoxor_w.S new file mode 100644 index 0000000..2b92323 --- /dev/null +++ b/isa/rv64ua/amoxor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xc0000001; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S new file mode 100644 index 0000000..6c4904e --- /dev/null +++ b/isa/rv64ua/lrsc.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + sc.w a4, x0, (a0); \ +) + +# make sure that sc with the wrong reservation fails. +TEST_CASE( 3, a4, 1, \ + la a0, foo; \ + add a1, a0, 1024; \ + lr.w a1, (a1); \ + sc.w a4, a1, (a0); \ +) + +# have each core add its coreid to foo 1000 times +la a0, foo +li a1, 1000 +1: lr.w a4, (a0) +add a4, a4, a2 +sc.w a4, a4, (a0) +bnez a4, 1b +add a1, a1, -1 +bnez a1, 1b + +# wait for all cores to finish +la a0, barrier +li a1, 1 +amoadd.w x0, a1, (a0) +1: lw a1, (a0) +blt a1, a3, 1b +fence + +# expected result is 1000*ncores*(ncores-1)/2 +TEST_CASE( 4, a2, 0, \ + la a0, foo; \ + li a1, 500; \ + mul a1, a1, a3; \ + add a2, a3, -1; \ + mul a1, a1, a2; \ + lw a2, (a0); \ + sub a2, a2, a1; \ +) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +coreid: .word 0 +barrier: .word 0 +foo: .word 0 +RVTEST_DATA_END |