Separate M, and A from I. Allow disabling of M,A,Ftravis-dev

This allows riscv-tests to be built with a compiler
that supports not just RVG.

12 files changed, 662 insertions, 0 deletions

diff --git a/isa/rv32um/Makefrag b/isa/rv32um/Makefrag
new file mode 100644
index 0000000..2094ccf
--- /dev/null
+++ b/isa/rv32um/Makefrag
@@ -0,0 +1,14 @@
+#=======================================================================
+# Makefrag for rv32um tests
+#-----------------------------------------------------------------------
+
+rv32um_sc_tests = \
+	div divu \
+	mul mulh mulhu mulhsu \
+	rem remu \
+
+rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
+rv32um_pt_tests = $(addprefix rv32um-pt-, $(rv32um_sc_tests))
+rv32um_pm_tests = $(addprefix rv32um-pm-, $(rv32um_mc_tests))
+
+spike_tests += $(rv32um_p_tests) $(rv32um_pt_tests) $(rv32um_pm_tests)
diff --git a/isa/rv32um/div.S b/isa/rv32um/div.S
new file mode 100644
index 0000000..a4504a7
--- /dev/null
+++ b/isa/rv32um/div.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, div,  3,  20,   6 );
+  TEST_RR_OP( 3, div, -3, -20,   6 );
+  TEST_RR_OP( 4, div, -3,  20,  -6 );
+  TEST_RR_OP( 5, div,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, div, -1<<63, -1<<63,  1 );
+  TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
+
+  TEST_RR_OP( 8, div, -1, -1<<63, 0 );
+  TEST_RR_OP( 9, div, -1,      1, 0 );
+  TEST_RR_OP(10, div, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/divu.S b/isa/rv32um/divu.S
new file mode 100644
index 0000000..cd348c9
--- /dev/null
+++ b/isa/rv32um/divu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divu,                   3,  20,   6 );
+  TEST_RR_OP( 3, divu,           715827879, -20,   6 );
+  TEST_RR_OP( 4, divu,                   0,  20,  -6 );
+  TEST_RR_OP( 5, divu,                   0, -20,  -6 );
+
+  TEST_RR_OP( 6, divu, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divu,     0,  -1<<31, -1 );
+
+  TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divu, -1,      1, 0 );
+  TEST_RR_OP(10, divu, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/divuw.S b/isa/rv32um/divuw.S
new file mode 100644
index 0000000..0868eeb
--- /dev/null
+++ b/isa/rv32um/divuw.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divuw.S
+#-----------------------------------------------------------------------------
+#
+# Test divuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divuw,         3,  20,   6 );
+  TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32,   6 );
+  TEST_RR_OP( 4, divuw,         0,  20,  -6 );
+  TEST_RR_OP( 5, divuw,         0, -20,  -6 );
+
+  TEST_RR_OP( 6, divuw, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divuw, 0,      -1<<31, -1 );
+
+  TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divuw, -1,      1, 0 );
+  TEST_RR_OP(10, divuw, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/divw.S b/isa/rv32um/divw.S
new file mode 100644
index 0000000..4d91749
--- /dev/null
+++ b/isa/rv32um/divw.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divw.S
+#-----------------------------------------------------------------------------
+#
+# Test divw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divw,  3,  20,   6 );
+  TEST_RR_OP( 3, divw, -3, -20,   6 );
+  TEST_RR_OP( 4, divw, -3,  20,  -6 );
+  TEST_RR_OP( 5, divw,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, divw, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divw, -1,      1, 0 );
+  TEST_RR_OP(10, divw, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/mul.S b/isa/rv32um/mul.S
new file mode 100644
index 0000000..0368629
--- /dev/null
+++ b/isa/rv32um/mul.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP(32,  mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
+  TEST_RR_OP(33,  mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
+
+  TEST_RR_OP( 2,  mul, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mul, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mul, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mul, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mul, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mul, 0x00000000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(34,  mul, 0x00000000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(35,  mul, 0x00000001, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(36,  mul, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(37,  mul, 0xffffffff, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mul, 0 );
+  TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/mulh.S b/isa/rv32um/mulh.S
new file mode 100644
index 0000000..e583f5f
--- /dev/null
+++ b/isa/rv32um/mulh.S
@@ -0,0 +1,81 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulh, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulh, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulh, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulh, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulh, 0x00000000, 0x80000000, 0x00000000 );
+
+  TEST_RR_OP(30,  mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulh, 0x00010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulh, 0x00000000, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulh, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulh, 0xffffffff, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulh, 0 );
+  TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/mulhsu.S b/isa/rv32um/mulhsu.S
new file mode 100644
index 0000000..28b3690
--- /dev/null
+++ b/isa/rv32um/mulhsu.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulhsu, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulhsu, 0xff010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulhsu, 0x00000000, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+  TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
+
+
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/mulhu.S b/isa/rv32um/mulhu.S
new file mode 100644
index 0000000..601dcff
--- /dev/null
+++ b/isa/rv32um/mulhu.S
@@ -0,0 +1,82 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhu, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulhu, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulhu, 0xfe010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulhu, 0x00000000, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulhu, 0x00000000, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+  TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
+
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/mulw.S b/isa/rv32um/mulw.S
new file mode 100644
index 0000000..577c93e
--- /dev/null
+++ b/isa/rv32um/mulw.S
@@ -0,0 +1,72 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulw.S
+#-----------------------------------------------------------------------------
+#
+# Test mulw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulw, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulw, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulw, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulw, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulw, 0x00000000, 0x80000000, 0xffff8000 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mulw, 0 );
+  TEST_RR_ZERODEST( 29, mulw, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/rem.S b/isa/rv32um/rem.S
new file mode 100644
index 0000000..c318e2c
--- /dev/null
+++ b/isa/rv32um/rem.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, rem,  2,  20,   6 );
+  TEST_RR_OP( 3, rem, -2, -20,   6 );
+  TEST_RR_OP( 4, rem,  2,  20,  -6 );
+  TEST_RR_OP( 5, rem, -2, -20,  -6 );
+
+  TEST_RR_OP( 6, rem,  0, -1<<63,  1 );
+  TEST_RR_OP( 7, rem,  0, -1<<63, -1 );
+
+  TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
+  TEST_RR_OP( 9, rem,      1,      1, 0 );
+  TEST_RR_OP(10, rem,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv32um/remu.S b/isa/rv32um/remu.S
new file mode 100644
index 0000000..38d641d
--- /dev/null
+++ b/isa/rv32um/remu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remu,   2,  20,   6 );
+  TEST_RR_OP( 3, remu,   2, -20,   6 );
+  TEST_RR_OP( 4, remu,  20,  20,  -6 );
+  TEST_RR_OP( 5, remu, -20, -20,  -6 );
+
+  TEST_RR_OP( 6, remu,      0, -1<<63,  1 );
+  TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
+
+  TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
+  TEST_RR_OP( 9, remu,      1,      1, 0 );
+  TEST_RR_OP(10, remu,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END