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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-04-29 23:45:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-04-29 23:45:34 -0700 |
| commit | 24d2144a30a06bea49ffd3010d43b152a5b50580 (patch) | |
| tree | 8cbfa654fb47da9eb7c2a33b154e9425ed91b8a0 /isa/rv32ui/amoand_w.S | |
| parent | 1f25cfbde65518f6e7b43d49451eb3ae1f9d2811 (diff) | |
| download | riscv-tests-24d2144a30a06bea49ffd3010d43b152a5b50580.zip riscv-tests-24d2144a30a06bea49ffd3010d43b152a5b50580.tar.gz riscv-tests-24d2144a30a06bea49ffd3010d43b152a5b50580.tar.bz2 | |
add first RV32 tests
Diffstat (limited to 'isa/rv32ui/amoand_w.S')
| -rw-r--r-- | isa/rv32ui/amoand_w.S | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/isa/rv32ui/amoand_w.S b/isa/rv32ui/amoand_w.S new file mode 100644 index 0000000..3204f1c --- /dev/null +++ b/isa/rv32ui/amoand_w.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x80000000, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 |