diff options
author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-04-29 23:45:34 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-04-29 23:45:34 -0700 |
commit | 24d2144a30a06bea49ffd3010d43b152a5b50580 (patch) | |
tree | 8cbfa654fb47da9eb7c2a33b154e9425ed91b8a0 /isa/rv32ui | |
parent | 1f25cfbde65518f6e7b43d49451eb3ae1f9d2811 (diff) | |
download | riscv-tests-24d2144a30a06bea49ffd3010d43b152a5b50580.zip riscv-tests-24d2144a30a06bea49ffd3010d43b152a5b50580.tar.gz riscv-tests-24d2144a30a06bea49ffd3010d43b152a5b50580.tar.bz2 |
add first RV32 tests
Diffstat (limited to 'isa/rv32ui')
-rw-r--r-- | isa/rv32ui/Makefrag | 33 | ||||
-rw-r--r-- | isa/rv32ui/add.S | 83 | ||||
-rw-r--r-- | isa/rv32ui/addi.S | 69 | ||||
-rw-r--r-- | isa/rv32ui/amoadd_w.S | 63 | ||||
-rw-r--r-- | isa/rv32ui/amoand_w.S | 63 | ||||
-rw-r--r-- | isa/rv32ui/amomax_w.S | 47 | ||||
-rw-r--r-- | isa/rv32ui/amomaxu_w.S | 47 | ||||
-rw-r--r-- | isa/rv32ui/amomin_w.S | 47 | ||||
-rw-r--r-- | isa/rv32ui/amominu_w.S | 47 | ||||
-rw-r--r-- | isa/rv32ui/amoor_w.S | 63 | ||||
-rw-r--r-- | isa/rv32ui/amoswap_w.S | 63 |
11 files changed, 625 insertions, 0 deletions
diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag new file mode 100644 index 0000000..b14f5a7 --- /dev/null +++ b/isa/rv32ui/Makefrag @@ -0,0 +1,33 @@ +#======================================================================= +# Makefrag for rv32ui tests +#----------------------------------------------------------------------- + +rv32ui_sc_tests = \ + add addi \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \ + #and andi \ + #auipc \ + #beq bge bgeu blt bltu bne \ + #div divu \ + #fence_i \ + #j jal jalr jalr_j jalr_r \ + #lb lbu lh lhu lw \ + #lui \ + #mul mulh mulhsu mulhu \ + #or ori \ + #rem remu \ + #sb sh sw \ + #sll slli \ + #slt slti \ + #sra srai \ + #srl srli \ + #sub \ + #xor xori \ + +rv32ui_mc_tests = \ + #lrsc + +rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests)) +rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests)) + +spike_tests += $(rv32ui_p_tests) $(rv32ui_pm_tests) diff --git a/isa/rv32ui/add.S b/isa/rv32ui/add.S new file mode 100644 index 0000000..38c0995 --- /dev/null +++ b/isa/rv32ui/add.S @@ -0,0 +1,83 @@ +#***************************************************************************** +# add.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, add, 0xffff8000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, add, 0x80000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, add, 0x7fff8000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 8, add, 0x00007fff, 0x00000000, 0x00007fff ); + TEST_RR_OP( 9, add, 0x7fffffff, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 10, add, 0x80007ffe, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 11, add, 0x80007fff, 0x80000000, 0x00007fff ); + TEST_RR_OP( 12, add, 0x7fff7fff, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 13, add, 0xffffffff, 0x00000000, 0xffffffff ); + TEST_RR_OP( 14, add, 0x00000000, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 15, add, 0xfffffffe, 0xffffffff, 0xffffffff ); + + TEST_RR_OP( 16, add, 0x80000000, 0x00000001, 0x7fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, add, 32, 32 ); + TEST_RR_ZEROSRC12( 37, add, 0 ); + TEST_RR_ZERODEST( 38, add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32ui/addi.S b/isa/rv32ui/addi.S new file mode 100644 index 0000000..96b2b3f --- /dev/null +++ b/isa/rv32ui/addi.S @@ -0,0 +1,69 @@ +#***************************************************************************** +# addi.S +#----------------------------------------------------------------------------- +# +# Test addi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 ); + TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 ); + TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 ); + + TEST_IMM_OP( 5, addi, 0xfffff800, 0x00000000, 0x800 ); + TEST_IMM_OP( 6, addi, 0x80000000, 0x80000000, 0x000 ); + TEST_IMM_OP( 7, addi, 0x7ffff800, 0x80000000, 0x800 ); + + TEST_IMM_OP( 8, addi, 0x000007ff, 0x00000000, 0x7ff ); + TEST_IMM_OP( 9, addi, 0x7fffffff, 0x7fffffff, 0x000 ); + TEST_IMM_OP( 10, addi, 0x800007fe, 0x7fffffff, 0x7ff ); + + TEST_IMM_OP( 11, addi, 0x800007ff, 0x80000000, 0x7ff ); + TEST_IMM_OP( 12, addi, 0x7ffff7ff, 0x7fffffff, 0x800 ); + + TEST_IMM_OP( 13, addi, 0xffffffff, 0x00000000, 0xfff ); + TEST_IMM_OP( 14, addi, 0x00000000, 0xffffffff, 0x001 ); + TEST_IMM_OP( 15, addi, 0xfffffffe, 0xffffffff, 0xfff ); + + TEST_IMM_OP( 16, addi, 0x80000000, 0x7fffffff, 0x001 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 ); + TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 ); + TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 ); + TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 ); + TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 ); + + TEST_IMM_ZEROSRC1( 24, addi, 32, 32 ); + TEST_IMM_ZERODEST( 25, addi, 33, 50 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32ui/amoadd_w.S b/isa/rv32ui/amoadd_w.S new file mode 100644 index 0000000..30d3f79 --- /dev/null +++ b/isa/rv32ui/amoadd_w.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ui/amoand_w.S b/isa/rv32ui/amoand_w.S new file mode 100644 index 0000000..3204f1c --- /dev/null +++ b/isa/rv32ui/amoand_w.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x80000000, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ui/amomax_w.S b/isa/rv32ui/amomax_w.S new file mode 100644 index 0000000..a7fc95a --- /dev/null +++ b/isa/rv32ui/amomax_w.S @@ -0,0 +1,47 @@ +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ui/amomaxu_w.S b/isa/rv32ui/amomaxu_w.S new file mode 100644 index 0000000..ca8045d --- /dev/null +++ b/isa/rv32ui/amomaxu_w.S @@ -0,0 +1,47 @@ +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ui/amomin_w.S b/isa/rv32ui/amomin_w.S new file mode 100644 index 0000000..3cbf08c --- /dev/null +++ b/isa/rv32ui/amomin_w.S @@ -0,0 +1,47 @@ +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ui/amominu_w.S b/isa/rv32ui/amominu_w.S new file mode 100644 index 0000000..3809d1c --- /dev/null +++ b/isa/rv32ui/amominu_w.S @@ -0,0 +1,47 @@ +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ui/amoor_w.S b/isa/rv32ui/amoor_w.S new file mode 100644 index 0000000..6df4da4 --- /dev/null +++ b/isa/rv32ui/amoor_w.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ui/amoswap_w.S b/isa/rv32ui/amoswap_w.S new file mode 100644 index 0000000..bf034d1 --- /dev/null +++ b/isa/rv32ui/amoswap_w.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffff800, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 |