Separate M, and A from I. Allow disabling of M,A,Ftravis-dev

This allows riscv-tests to be built with a compiler
that supports not just RVG.

10 files changed, 554 insertions, 0 deletions

diff --git a/isa/rv32ua/Makefrag b/isa/rv32ua/Makefrag
new file mode 100644
index 0000000..1846506
--- /dev/null
+++ b/isa/rv32ua/Makefrag
@@ -0,0 +1,15 @@
+#=======================================================================
+# Makefrag for rv32ua tests
+#-----------------------------------------------------------------------
+
+rv32ua_sc_tests = \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
+
+rv32ua_mc_tests = \
+	lrsc
+
+rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests))
+rv32ua_pt_tests = $(addprefix rv32ua-pt-, $(rv32ua_sc_tests))
+rv32ua_pm_tests = $(addprefix rv32ua-pm-, $(rv32ua_mc_tests))
+
+spike_tests += $(rv32ua_p_tests) $(rv32ua_pt_tests) $(rv32ua_pm_tests)
diff --git a/isa/rv32ua/amoadd_w.S b/isa/rv32ua/amoadd_w.S
new file mode 100644
index 0000000..975ae1d
--- /dev/null
+++ b/isa/rv32ua/amoadd_w.S
@@ -0,0 +1,65 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoadd.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x7ffff800, \
+    li  a1, 0x80000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoadd.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+    .bss
+    .align 3
+amo_operand:
+    .dword 0
+    .skip 65536
diff --git a/isa/rv32ua/amoand_w.S b/isa/rv32ua/amoand_w.S
new file mode 100644
index 0000000..7c989c2
--- /dev/null
+++ b/isa/rv32ua/amoand_w.S
@@ -0,0 +1,65 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoand.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x80000000, \
+    li  a1, 0x80000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoand.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ua/amomax_w.S b/isa/rv32ua/amomax_w.S
new file mode 100644
index 0000000..698cf26
--- /dev/null
+++ b/isa/rv32ua/amomax_w.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 1; \
+    sw x0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 1, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ua/amomaxu_w.S b/isa/rv32ua/amomaxu_w.S
new file mode 100644
index 0000000..27c4ddf
--- /dev/null
+++ b/isa/rv32ua/amomaxu_w.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomaxu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffff; \
+    sw x0, 0(a3); \
+    amomaxu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ua/amomin_w.S b/isa/rv32ua/amomin_w.S
new file mode 100644
index 0000000..a6a0947
--- /dev/null
+++ b/isa/rv32ua/amomin_w.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomin.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffff; \
+    sw x0, 0(a3); \
+    amomin.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ua/amominu_w.S b/isa/rv32ua/amominu_w.S
new file mode 100644
index 0000000..ce06e1c
--- /dev/null
+++ b/isa/rv32ua/amominu_w.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amominu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffff; \
+    sw x0, 0(a3); \
+    amominu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ua/amoor_w.S b/isa/rv32ua/amoor_w.S
new file mode 100644
index 0000000..0988c66
--- /dev/null
+++ b/isa/rv32ua/amoor_w.S
@@ -0,0 +1,65 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoor.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffff800, \
+    li  a1, 1; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoor.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ua/amoswap_w.S b/isa/rv32ua/amoswap_w.S
new file mode 100644
index 0000000..a32ae74
--- /dev/null
+++ b/isa/rv32ua/amoswap_w.S
@@ -0,0 +1,65 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoswap.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffff800, \
+    li  a1, 0x80000000; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoswap.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536
diff --git a/isa/rv32ua/lrsc.S b/isa/rv32ua/lrsc.S
new file mode 100644
index 0000000..2aee818
--- /dev/null
+++ b/isa/rv32ua/lrsc.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+#
+# Test LR/SC instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+# get a unique core id
+la a0, coreid
+li a1, 1
+amoadd.w a2, a1, (a0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
+1: lw a1, (a0)
+bltu a1, a3, 1b
+
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+  la a0, foo; \
+  sc.w a4, x0, (a0); \
+)
+
+# make sure that sc with the wrong reservation fails.
+TEST_CASE( 3, a4, 1, \
+  la a0, foo; \
+  add a1, a0, 1024; \
+  lr.w a1, (a1); \
+  sc.w a4, a1, (a0); \
+)
+
+# have each core add its coreid to foo 1000 times
+la a0, foo
+li a1, 1000
+1: lr.w a4, (a0)
+add a4, a4, a2
+sc.w a4, a4, (a0)
+bnez a4, 1b
+add a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores to finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+fence
+
+# expected result is 1000*ncores*(ncores-1)/2
+TEST_CASE( 4, a2, 0, \
+  la a0, foo; \
+  li a1, 500; \
+  mul a1, a1, a3; \
+  add a2, a3, -1; \
+  mul a1, a1, a2; \
+  lw a2, (a0); \
+  sub a2, a2, a1; \
+)
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+RVTEST_DATA_END