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2020-01-09rvv: add vfxxx.vf float64 supportChih-Min Chao23-3/+79
2020-01-09rvv: add vfxxx.vv float64 suuportChih-Min Chao22-5/+75
2019-12-20rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao3-14/+37
2019-12-20rvv: refine fault-first loopChih-Min Chao1-2/+1
2019-12-20rvv: make vlx/vsx match 0.8 specChih-Min Chao12-42/+49
2019-12-20rvv: change vmerge/vslideup register checking ruleChih-Min Chao7-3/+7
2019-12-20rvv: change vsetvl[i] to match 0.8 specChih-Min Chao4-8/+8
2019-12-20rvv: remove unsupported widen sewChih-Min Chao1-6/+0
2019-12-20rvv: fix vmadc/vmsbcChih-Min Chao6-9/+11
2019-12-20rvv: fix vadc/vsbcChih-Min Chao6-16/+65
2019-12-20rvv: add unsigned averageChih-Min Chao6-0/+52
2019-12-20rvv: replace vn suffic by 'w'Chih-Min Chao14-48/+48
2019-12-20rvv: fix floating sign inject operand orderChih-Min Chao6-6/+6
2019-12-20rvv: add load/store whole register instructionsChih-Min Chao4-0/+28
2019-12-20rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao8-26/+34
2019-12-20rvv: add vqm* 'Quad-Widening Integer Multiply-Add'Chih-Min Chao16-124/+108
2019-12-20rvv: add quad insn and new vlenb csrChih-Min Chao4-29/+30
2019-12-19Merge pull request #371 from riscv/fix-vlffAndrew Waterman2-66/+28
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls3-11/+33
2019-12-16Set vstart correctly for vector loads/storesAndrew Waterman1-0/+2
2019-12-16Detect too-long segment before starting a vector loadAndrew Waterman1-4/+2
2019-12-16Fix first-fault load exception behaviorAndrew Waterman1-3/+13
2019-12-16Simplify vleff.v implementation in the same way as vle.vAndrew Waterman1-53/+11
2019-12-16Don't terminate first-fault loads on zero data valuesAndrew Waterman1-6/+0
2019-12-06Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna2-1/+3
2019-11-27Initialize mtimeAndrew Waterman1-1/+1
2019-11-27Fix (benign) uninitialized variableAndrew Waterman1-1/+1
2019-11-24Initialize state.misa prior to calls to supports_extensionAndrew Waterman1-0/+2
2019-11-15Re-encode vaadd/vasub; remove vaadd.vi; add vaaddu/vasubuAndrew Waterman2-44/+55
2019-11-12mstatus.FS only exists if (S || V || F)Andrew Waterman1-1/+5
2019-11-12Remove S-mode interrupts when S-mode not presentAndrew Waterman1-5/+12
2019-11-12Fix mode-transition logic when S-mode not presentAndrew Waterman1-1/+1
2019-11-12SRET requires S-modeAndrew Waterman1-0/+1
2019-11-12Remove S-mode CSRs when S-mode is not presentAndrew Waterman1-1/+2
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman5-10/+44
2019-11-12Factor out boilerplate strtolower functionAndrew Waterman1-3/+9
2019-11-12In parse_isa_string, populate max_isa rather than state.misaAndrew Waterman1-7/+3
2019-11-11rvv: add 'V' ext check for each vector insnChih-Min Chao1-1/+1
2019-11-11rvv: fix reg checking for vmadc/vmsbcChih-Min Chao5-5/+0
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao14-79/+51
2019-11-11rvv: add reg checking rule to vslide instructionsChih-Min Chao6-10/+37
2019-11-11rvv: add reg checking rule for ldstChih-Min Chao17-8/+32
2019-11-11rvv: add reg checking rule for general fomratChih-Min Chao18-5/+38
2019-11-11rvv: add reg checking rule for comparison instrucitonsChih-Min Chao11-11/+29
2019-11-11rvv: add reg checking rule for reductionChih-Min Chao1-5/+12
2019-11-11rvv: add register using check for wide and narrow insnChih-Min Chao19-51/+66
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao2-5/+18
2019-11-11rvv: fix vsmul sign and variable typeChih-Min Chao2-25/+23
2019-11-11rvv: fix vssr/vssra rounding issueChih-Min Chao6-12/+19
2019-11-11rvv: fix the rounding bit position for vnclip instructions.Albert Ou6-50/+34
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