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AgeCommit message (Expand)AuthorFilesLines
2020-02-06Fix incorrect commentsAndrew Waterman2-2/+2
2020-01-30Fix pmpcfg0 initial value regression from cb254bfab5fbb6d69e5dd336798861e7c11...Andrew Waterman1-5/+5
2020-01-29Initialize PMPs with set_csr to fix WARLness of initial valueAndrew Waterman1-3/+6
2020-01-24Prevent pmpaddr* and satp from holding invalid physical addressesAndrew Waterman1-2/+3
2020-01-24rvv: fix corner case when input are 1's and shift amount is maximumChih-Min Chao2-2/+2
2020-01-24rvv: remove duplicate vectorUnit declarationChih-Min Chao1-54/+0
2020-01-22commitlog: rvv: add commitlog support to misc instrutionsChih-Min Chao7-16/+16
2020-01-22commitlog: rvv: add commitlog support to integer instructionsChih-Min Chao2-37/+37
2020-01-22commitlog: rvv: add commitlog support to float instrunctionsChih-Min Chao15-31/+30
2020-01-22commitlog: rvv: add commitlog support to load instructionsChih-Min Chao1-8/+9
2020-01-22commitlog: rvv: change vector register read/write interfaceChih-Min Chao3-2/+65
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao4-23/+61
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao4-24/+17
2020-01-13state: rewrite state_t initializationChih-Min Chao2-5/+59
2020-01-13Make minimum RTI behavior more realistic. (#375)Tim Newsome1-32/+35
2020-01-13Expose sstatus.vs fieldAndrew Waterman1-0/+1
2020-01-13rvv: segment load/store needs to check destination rangeChih-Min Chao1-2/+3
2020-01-13rvv: add vmv[1248]r.vChih-Min Chao8-2/+36
2020-01-13rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao12-14/+51
2020-01-09rvv: refinve vfmv to support float64Chih-Min Chao4-29/+62
2020-01-09rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 supportChih-Min Chao7-12/+48
2020-01-09rvv: add vmfxxx.v[vf] float64 supportChih-Min Chao11-26/+85
2020-01-09rvv: add vfxxx.vf float64 supportChih-Min Chao23-3/+79
2020-01-09rvv: add vfxxx.vv float64 suuportChih-Min Chao22-5/+75
2019-12-20rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao3-14/+37
2019-12-20rvv: refine fault-first loopChih-Min Chao1-2/+1
2019-12-20rvv: make vlx/vsx match 0.8 specChih-Min Chao12-42/+49
2019-12-20rvv: change vmerge/vslideup register checking ruleChih-Min Chao7-3/+7
2019-12-20rvv: change vsetvl[i] to match 0.8 specChih-Min Chao4-8/+8
2019-12-20rvv: remove unsupported widen sewChih-Min Chao1-6/+0
2019-12-20rvv: fix vmadc/vmsbcChih-Min Chao6-9/+11
2019-12-20rvv: fix vadc/vsbcChih-Min Chao6-16/+65
2019-12-20rvv: add unsigned averageChih-Min Chao6-0/+52
2019-12-20rvv: replace vn suffic by 'w'Chih-Min Chao14-48/+48
2019-12-20rvv: fix floating sign inject operand orderChih-Min Chao6-6/+6
2019-12-20rvv: add load/store whole register instructionsChih-Min Chao4-0/+28
2019-12-20rvv: rename vfncvt suffix and add rod rouding typeChih-Min Chao8-26/+34
2019-12-20rvv: add vqm* 'Quad-Widening Integer Multiply-Add'Chih-Min Chao16-124/+108
2019-12-20rvv: add quad insn and new vlenb csrChih-Min Chao4-29/+30
2019-12-19Merge pull request #371 from riscv/fix-vlffAndrew Waterman2-66/+28
2019-12-16extend the commit and memory writes log feature with memory reads (#370)John Ingalls3-11/+33
2019-12-16Set vstart correctly for vector loads/storesAndrew Waterman1-0/+2
2019-12-16Detect too-long segment before starting a vector loadAndrew Waterman1-4/+2
2019-12-16Fix first-fault load exception behaviorAndrew Waterman1-3/+13
2019-12-16Simplify vleff.v implementation in the same way as vle.vAndrew Waterman1-53/+11
2019-12-16Don't terminate first-fault loads on zero data valuesAndrew Waterman1-6/+0
2019-12-06Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna2-1/+3
2019-11-27Initialize mtimeAndrew Waterman1-1/+1
2019-11-27Fix (benign) uninitialized variableAndrew Waterman1-1/+1
2019-11-24Initialize state.misa prior to calls to supports_extensionAndrew Waterman1-0/+2
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