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AgeCommit message (Expand)AuthorFilesLines
2020-02-20commitlog: print vsew in bitChih-Min Chao1-1/+1
2020-02-20rvv: don't zero vstart in the beginningChih-Min Chao1-1/+0
2020-02-18widening reductions are legal when LMUL=8Andrew Waterman1-1/+0
2020-02-18Vector stores don't care if rd overlaps v0 (#400)Andrew Waterman5-13/+20
2020-02-18Merge pull request #396 from chihminchao/rvv-fix-2020-02-14Andrew Waterman17-25/+31
2020-02-18commitlog: fix printf format warningChih-Min Chao1-1/+1
2020-02-18rvv: make variable name match its meaningChih-Min Chao4-4/+4
2020-02-18rvv: fix vmsleu/vmsgtu/vsaddu.vi operand signed extensionChih-Min Chao3-3/+3
2020-02-17v[f]merge: allow v0 overlap if LMUL = 1Andrew Waterman2-2/+0
2020-02-17vadc/vsbc: allow v0 overlap if LMUL = 1Andrew Waterman1-2/+2
2020-02-15Make CLINT API use Hz instead of MHzAndrew Waterman3-6/+6
2020-02-15Add optional support for real-time clintAnup Patel4-7/+30
2020-02-14rvv: fix exception rethrow in fault-first loadChih-Min Chao1-1/+1
2020-02-14rvv: reset vstart to 0 when vmv.s.x and vmv.x.s and also check the vstart < v...Dave.Wen2-1/+5
2020-02-14rvv: respect vstart in fault-first loadChih-Min Chao1-3/+3
2020-02-14rvv: vms[bio]f.m need to start from 0Chih-Min Chao3-6/+3
2020-02-14rvv: vsbc/vmsbc behavior of the sub orderMax Lin4-4/+4
2020-02-14rvv: fix Vxrm not reflected in fcsrDave.Wen1-2/+7
2020-02-14Make spike capable of booting LinuxAnup Patel4-4/+17
2020-02-12Improve --varch error checking. (#394)Tim Newsome2-10/+20
2020-02-06Fix incorrect commentsAndrew Waterman2-2/+2
2020-01-30Fix pmpcfg0 initial value regression from cb254bfab5fbb6d69e5dd336798861e7c11...Andrew Waterman1-5/+5
2020-01-29Initialize PMPs with set_csr to fix WARLness of initial valueAndrew Waterman1-3/+6
2020-01-24Prevent pmpaddr* and satp from holding invalid physical addressesAndrew Waterman1-2/+3
2020-01-24rvv: fix corner case when input are 1's and shift amount is maximumChih-Min Chao2-2/+2
2020-01-24rvv: remove duplicate vectorUnit declarationChih-Min Chao1-54/+0
2020-01-22commitlog: rvv: add commitlog support to misc instrutionsChih-Min Chao7-16/+16
2020-01-22commitlog: rvv: add commitlog support to integer instructionsChih-Min Chao2-37/+37
2020-01-22commitlog: rvv: add commitlog support to float instrunctionsChih-Min Chao15-31/+30
2020-01-22commitlog: rvv: add commitlog support to load instructionsChih-Min Chao1-8/+9
2020-01-22commitlog: rvv: change vector register read/write interfaceChih-Min Chao3-2/+65
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao4-23/+61
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao4-24/+17
2020-01-13state: rewrite state_t initializationChih-Min Chao2-5/+59
2020-01-13Make minimum RTI behavior more realistic. (#375)Tim Newsome1-32/+35
2020-01-13Expose sstatus.vs fieldAndrew Waterman1-0/+1
2020-01-13rvv: segment load/store needs to check destination rangeChih-Min Chao1-2/+3
2020-01-13rvv: add vmv[1248]r.vChih-Min Chao8-2/+36
2020-01-13rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao12-14/+51
2020-01-09rvv: refinve vfmv to support float64Chih-Min Chao4-29/+62
2020-01-09rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 supportChih-Min Chao7-12/+48
2020-01-09rvv: add vmfxxx.v[vf] float64 supportChih-Min Chao11-26/+85
2020-01-09rvv: add vfxxx.vf float64 supportChih-Min Chao23-3/+79
2020-01-09rvv: add vfxxx.vv float64 suuportChih-Min Chao22-5/+75
2019-12-20rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao3-14/+37
2019-12-20rvv: refine fault-first loopChih-Min Chao1-2/+1
2019-12-20rvv: make vlx/vsx match 0.8 specChih-Min Chao12-42/+49
2019-12-20rvv: change vmerge/vslideup register checking ruleChih-Min Chao7-3/+7
2019-12-20rvv: change vsetvl[i] to match 0.8 specChih-Min Chao4-8/+8
2019-12-20rvv: remove unsupported widen sewChih-Min Chao1-6/+0
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