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2020-02-18Merge pull request #396 from chihminchao/rvv-fix-2020-02-14Andrew Waterman1-2/+7
2020-02-14rvv: fix Vxrm not reflected in fcsrDave.Wen1-2/+7
2020-02-12Improve --varch error checking. (#394)Tim Newsome1-8/+18
2020-01-30Fix pmpcfg0 initial value regression from cb254bfab5fbb6d69e5dd336798861e7c11...Andrew Waterman1-5/+5
2020-01-29Initialize PMPs with set_csr to fix WARLness of initial valueAndrew Waterman1-3/+6
2020-01-24Prevent pmpaddr* and satp from holding invalid physical addressesAndrew Waterman1-2/+3
2020-01-22commitlog: rvv: change vector register read/write interfaceChih-Min Chao1-2/+2
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao1-1/+1
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao1-2/+2
2020-01-13state: rewrite state_t initializationChih-Min Chao1-5/+51
2020-01-13Expose sstatus.vs fieldAndrew Waterman1-0/+1
2019-12-20rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao1-11/+14
2019-12-20rvv: change vsetvl[i] to match 0.8 specChih-Min Chao1-5/+5
2019-12-20rvv: add quad insn and new vlenb csrChih-Min Chao1-0/+6
2019-12-06Require VM enabled for SFENCE.VMA and S-mode for mstatus.SUM (#367)Udit Khanna1-1/+2
2019-11-27Fix (benign) uninitialized variableAndrew Waterman1-1/+1
2019-11-24Initialize state.misa prior to calls to supports_extensionAndrew Waterman1-0/+2
2019-11-12mstatus.FS only exists if (S || V || F)Andrew Waterman1-1/+5
2019-11-12Remove S-mode interrupts when S-mode not presentAndrew Waterman1-5/+12
2019-11-12Fix mode-transition logic when S-mode not presentAndrew Waterman1-1/+1
2019-11-12Add --priv option to control which privilege modes are availableAndrew Waterman1-2/+27
2019-11-12Factor out boilerplate strtolower functionAndrew Waterman1-3/+9
2019-11-12In parse_isa_string, populate max_isa rather than state.misaAndrew Waterman1-7/+3
2019-11-11rvv: refine vsetvl[i] logicChih-Min Chao1-4/+17
2019-10-24Initialize histogram_enabled and log_commits_enabled in constructor (#354)Scott Johnson1-0/+1
2019-09-18Adds --log-commits commandline option. (#323)dave-estes-syzexion1-0/+13
2019-08-23Remove statement with no effectAndrew Waterman1-1/+0
2019-07-19Set vtype.vill correctly; also reset it to trueAndrew Waterman1-3/+8
2019-07-19Check presence of V extension when accessing vector CSRsAndrew Waterman1-0/+15
2019-07-19VL and VTYPE aren't writable CSRsAndrew Waterman1-12/+0
2019-07-16Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)Tim Newsome1-2/+7
2019-07-12Add debug_mode state bit, rather than overloading dcsr.causeAndrew Waterman1-4/+5
2019-07-11Fix support for 32-bit hosts (but no V extension in that case!)Andrew Waterman1-1/+5
2019-07-11Support S-mode vectored interruptsAndrew Waterman1-2/+3
2019-07-05Fix clang uninitialized variable warningAndrew Waterman1-1/+1
2019-06-18rvv: add control instructions and system register accessChih-Min Chao1-0/+31
2019-06-14rvv: add varch option parser and initialize vector unitChih-Min Chao1-4/+67
2019-06-14rvv: add vector unit structureChih-Min Chao1-0/+26
2019-03-30RV32Q is not invalidAndrew Waterman1-3/+0
2019-03-27Respect interrupt priorities even when not delegatedAndrew Waterman1-9/+13
2019-02-04Fix use of old name `riscv-isa-run` (#269)Luís Marques1-1/+1
2018-12-21Reserve the PMP R=0 W=1 combinationAndrew Waterman1-2/+5
2018-10-04Set marchid to assigned value 5Andrew Waterman1-1/+1
2018-09-27Add comment about CSR read side effectsAndrew Waterman1-0/+3
2018-09-25For backwards compatibility, reset PMP to permit all accessesAndrew Waterman1-0/+3
2018-09-25Add PMP supportAndrew Waterman1-0/+32
2018-08-22Make IRQ_COP read-only/undelegable unless coprocessor is presentAndrew Waterman1-1/+2
2018-08-21Instantiate disassembler after max_xlen is knownAndrew Waterman1-1/+5
2018-08-17Don't increment instret immediately after it is written (#231)Andrew Waterman1-0/+6
2018-07-31Make sstatus.MXR readableAndrew Waterman1-1/+1
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