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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-27 15:36:39 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-11-27 15:38:20 -0800 |
| commit | 1f34121c901164b6e11d4190833026224a6ff1cb (patch) | |
| tree | 4247bdbde3bdd9ad1f1b6eebf7a99a3985bba111 /riscv/processor.cc | |
| parent | b36b0d66d9357b0c1f52a20233196efcd3ab2404 (diff) | |
| download | riscv-isa-sim-1f34121c901164b6e11d4190833026224a6ff1cb.zip riscv-isa-sim-1f34121c901164b6e11d4190833026224a6ff1cb.tar.gz riscv-isa-sim-1f34121c901164b6e11d4190833026224a6ff1cb.tar.bz2 | |
Fix (benign) uninitialized variable
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index e8bafcd..9b40c63 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -22,7 +22,7 @@ processor_t::processor_t(const char* isa, const char* priv, const char* varch, simif_t* sim, uint32_t id, bool halt_on_reset) - : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), + : debug(false), halt_request(false), sim(sim), ext(NULL), id(id), xlen(0), histogram_enabled(false), log_commits_enabled(false), halt_on_reset(halt_on_reset), last_pc(1), executions(1) { |