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AgeCommit message (Expand)AuthorFilesLines
2023-01-03Pass cfg object to processor_t constructorAndrew Waterman1-5/+4
2022-12-27Prevent processor_t from retiring instructions after a WFIJerry Zhao1-0/+4
2022-12-21Merge pull request #1192 from riscv-software-src/improve-histogramAndrew Waterman1-2/+6
2022-12-21Sort histogram printout count, rather than addressAndrew Waterman1-2/+6
2022-12-21Remove --enable-histogram optionAndrew Waterman1-7/+0
2022-12-21Support histogram regardless of configure flagAndrew Waterman1-2/+0
2022-12-20Always build with commit logging supportJerry Zhao1-8/+0
2022-12-20Add logged instruction variants to insn_desc_tJerry Zhao1-3/+12
2022-12-20Add logged variants of insn templatesJerry Zhao1-8/+8
2022-12-20Always reset commit logging variablesJerry Zhao1-2/+0
2022-12-20Always perform symbol lookup in debugJerry Zhao1-2/+5
2022-12-15Rename memif_endianness_t to endianness_tJerry Zhao1-1/+1
2022-12-13Merge pull request #1173 from ucb-bar/splitvuAndrew Waterman1-61/+1
2022-12-12Make the processor_t interface independent of configure'd variables (#1174)Jerry Zhao1-2/+8
2022-12-12Pull vector unit into separate source/headerJerry Zhao1-61/+1
2022-12-10triggers: add mcontext and hcontext CSRsYenHaoChen1-0/+3
2022-12-10triggers: add scontext CSRYenHaoChen1-0/+2
2022-12-09refactor: add tdata3_csr_t; preparation for CSR textraYenHaoChen1-1/+1
2022-12-05Merge pull request #1155 from YenHaoChen/pr-h-not-constScott Johnson1-6/+2
2022-12-05add macro N_HPMCOUNTERS (29)YenHaoChen1-1/+1
2022-12-05refactor: add custom CSR class, mevent_csr_tYenHaoChen1-5/+1
2022-12-01triggers: add debug log of trigger actionYenHaoChen1-0/+7
2022-12-01triggers: refactor: add take_trigger_action() to processor.h/processor.ccYenHaoChen1-0/+16
2022-11-29triggers: rename storeTim Newsome1-1/+1
2022-11-29Triggers: rename loadTim Newsome1-1/+1
2022-11-23Triggers rename executeTim Newsome1-1/+1
2022-11-22Add tinfo register.Tim Newsome1-0/+1
2022-11-17add support for zcmtWeiwei Li1-1/+6
2022-11-17add support for zca zcd and zcfWeiwei Li1-1/+1
2022-10-26Merge pull request #1133 from YenHaoChen/pr-sscofpmf-meventAndrew Waterman1-2/+4
2022-10-26fix mevent_mask for Sscofpmf extensionYenHaoChen1-2/+4
2022-10-25Remove set_target_endianness | add --big-endian flagJerry Zhao1-1/+2
2022-10-17fix clang buildAndrew Waterman1-1/+1
2022-10-17Add command to display privilege level in interactive modeJerry Zhao1-0/+18
2022-10-04Silence unused-variable warnings in auto-generated codeAndrew Waterman1-0/+4
2022-10-04Suppress most unused variable warningsAndrew Waterman1-1/+1
2022-09-20Merge pull request #1036 from plctlab/plct-sscofpmf-devAndrew Waterman1-3/+16
2022-08-28Fix tval on illegal instruction faults with long illegal instructionYenHaoChen1-1/+4
2022-08-10Improve write log for vtype in set_vlWeiwei Li1-1/+2
2022-08-10Fix code indentation in processor.cc, interactive.cc, debug_module.h/ccWeiwei Li1-1/+1
2022-08-09modify take_interrupt to support LCOFIP irqWeiwei Li1-0/+2
2022-08-09add support for sscofpmf extension v0.5.2Weiwei Li1-3/+14
2022-08-08Merge pull request #1059 from plctlab/plct-stateen-fixAndrew Waterman1-1/+1
2022-08-03Add Sstc support. (#1057)i2h21-3/+20
2022-08-03add stateen related check to frm/fflags and then apply to fcsr implicitlyWeiwei Li1-1/+1
2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman1-5/+21
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li1-0/+11
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li1-5/+10
2022-07-17add U mode check for *envcfg*Weiwei Li1-24/+26
2022-07-14add support for mconfigptr csr: it's hardwired to zero currentlyWeiwei Li1-1/+1
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