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mmu.cc
Age
Commit message (
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Author
Files
Lines
2021-07-22
Non-leaf PTEs with D/A/U==1 are reserved
Andrew Waterman
1
-0
/
+2
2021-07-22
Merge branch 'nonleaf_dau' of https://github.com/daniellustig/riscv-isa-sim i...
Andrew Waterman
1
-0
/
+2
2021-07-22
Non-leaf PTEs with D/A/U==1 are reserved
Dan Lustig
1
-0
/
+2
2021-07-21
Fix hypervisor MXR and SUM
Andrew Waterman
1
-8
/
+10
2021-07-21
Fix HLVX permissions check
Andrew Waterman
1
-15
/
+13
2021-07-21
Simplify (and possibly fix) handling of HLV/HSV TLB accesses
Andrew Waterman
1
-2
/
+2
2021-07-21
HLV/HSV instructions should respect SPVP even in debug mode
Andrew Waterman
1
-1
/
+1
2021-07-20
Priv virtual memory updates (#750)
Daniel Lustig
1
-4
/
+8
2021-07-16
Fix MPRV-related bug
Andrew Waterman
1
-1
/
+5
2021-03-05
Don't make MPRV load/store virtual if MPV=1, MPP=3 (#666)
jameshippisley
1
-1
/
+1
2021-02-08
Zsn has been renamed Svnapot (#641)
Daniel Lustig
1
-1
/
+1
2020-12-18
Check and use proc variable in MMU emulation
Anup Patel
1
-3
/
+3
2020-12-07
Oops...napot_bits should use ctz, not clz (#614)
Daniel Lustig
1
-2
/
+2
2020-11-27
Fix hstatus.GVA and mstatus.GVA updation
Anup Patel
1
-15
/
+15
2020-11-18
Don't include PTE.N bit as part of the PPN
Andrew Waterman
1
-2
/
+2
2020-11-18
Invalid NAPOT settings cause page faults, not access exceptions
Andrew Waterman
1
-2
/
+2
2020-11-18
Add Zsn extension
Andrew Waterman
1
-3
/
+18
2020-11-07
Tag target endian values to help guide conversion code
Marcus Comstedt
1
-4
/
+4
2020-11-07
Implement support for big-endian targets
Marcus Comstedt
1
-4
/
+7
2020-10-24
Fix trap generation in s2xlate()
Anup Patel
1
-7
/
+7
2020-07-09
Implement hypervisor two-stage MMU
Anup Patel
1
-15
/
+95
2020-07-08
Extend trap classes to pass more information
Anup Patel
1
-9
/
+9
2020-05-10
Implement coarse-grain PMP matching logic
Andrew Waterman
1
-6
/
+6
2020-05-10
Disable PMP checks when configuration includes zero PMP registers
Andrew Waterman
1
-1
/
+1
2020-05-09
Rename n_pmp constant to max_pmp
Andrew Waterman
1
-2
/
+2
2020-02-21
Allow debug accesses from MMUs not bound to processors
Andrew Waterman
1
-1
/
+1
2020-02-20
Disallow access to debug memory region unless in debug mode
Andrew Waterman
1
-3
/
+28
2019-10-28
Implement support for big-endian hosts
Marcus Comstedt
1
-2
/
+2
2019-07-12
Add debug_mode state bit, rather than overloading dcsr.cause
Andrew Waterman
1
-1
/
+1
2019-02-28
Further fix PMP checks for partially-matching accesses (#270)
Andrew Waterman
1
-3
/
+4
2019-01-28
Fix PMP checks for partially-matching accesses (#270)
Andrew Waterman
1
-7
/
+20
2018-09-25
Add PMP support
Andrew Waterman
1
-21
/
+105
2018-07-10
Refactor and fix LR/SC implementation (#217)
Andrew Waterman
1
-0
/
+1
2018-05-31
Put simif_t declaration in its own file. (#209)
Andy Wright
1
-1
/
+1
2018-03-21
Fix the access exception during page-table walks to match the original access...
Prashanth Mundkur
1
-1
/
+9
2018-03-06
Narrow the interface used by the processors and memory to the top-level simul...
Prashanth Mundkur
1
-1
/
+1
2017-11-27
Rename sptbr to satp
Andrew Waterman
1
-1
/
+1
2017-06-07
Forbid S-mode execution from user memory
Andrew Waterman
1
-2
/
+2
2017-05-05
Trap superpage PTEs when PPN LSBs are set
Andrew Waterman
1
-0
/
+2
2017-04-30
Store both host & target address in soft TLB
Andrew Waterman
1
-16
/
+17
2017-03-27
Separate page faults from physical memory access exceptions
Andrew Waterman
1
-4
/
+4
2017-03-20
PUM -> SUM; expose MXR to S-mode
Andrew Waterman
1
-2
/
+2
2017-02-18
Make HW setting of PTE A/D bits optional (by configure arg)
Andrew Waterman
1
-1
/
+8
2017-02-08
Encode VM type in sptbr, not mstatus
Andrew Waterman
1
-29
/
+18
2016-09-02
Support triggers on TLB misses.
Tim Newsome
1
-0
/
+42
2016-08-22
Implement address and data triggers.
Tim Newsome
1
-4
/
+16
2016-07-12
Fix page table walker not respecting valid bit
Andrew Waterman
1
-1
/
+1
2016-07-06
Update to new PTE format
Andrew Waterman
1
-8
/
+14
2016-05-23
Turn off debugging.
Tim Newsome
1
-9
/
+0
2016-05-23
Ignore MPRV in Debug Mode.
Tim Newsome
1
-1
/
+1
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