aboutsummaryrefslogtreecommitdiff
path: root/riscv/insns
AgeCommit message (Expand)AuthorFilesLines
2013-09-27Use WRITE_RD/WRITE_FRD macros to write registersAndrew Waterman139-162/+162
2013-09-21Update ISA encoding and AUIPC semanticsAndrew Waterman1-1/+1
2013-09-11Add AMOXORAndrew Waterman2-0/+7
2013-09-11Implement zany immediatesAndrew Waterman32-32/+32
2013-09-10Add rd field to JAL; drop JAndrew Waterman2-2/+1
2013-08-11Instructions are no longer member functionsAndrew Waterman51-78/+84
2013-08-08Ignore JALR's effective address LSBAndrew Waterman1-1/+1
2013-08-08Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman2-0/+0
2013-07-31Fix eret (again)Quan Nguyen1-1/+1
2013-07-31Fix dumb ERET bugAndrew Waterman1-1/+1
2013-07-26New supervisor modeAndrew Waterman1-3/+3
2013-07-26Rename MFTX/MXTF to FMVAndrew Waterman4-0/+0
2013-07-26Rip out Hwacha for nowAndrew Waterman90-145/+0
2013-07-26Rip out RVC for nowAndrew Waterman34-101/+0
2013-07-25Remove JALR static hintsAndrew Waterman3-2/+0
2013-04-17add AUIPC insn; remove RDNPC insnAndrew Waterman2-1/+1
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman4-0/+6
2013-03-25truncate effective addresses in rv32Andrew Waterman16-16/+16
2012-08-30new tohost/fromhost semanticsAndrew Waterman1-2/+1
2012-08-01new tohost/fromhost semanticsAndrew Waterman1-1/+2
2012-03-24new supervisor modeAndrew Waterman7-109/+13
2012-03-19make NaN behavior consistent with hardfloatAndrew Waterman10-10/+10
2012-03-18update vector fencesAndrew Waterman4-0/+0
2012-03-18clean up vector exception instructionsYunsup Lee2-0/+0
2012-03-13add more instructions for vector exception handlingYunsup Lee4-0/+0
2012-03-13add vvcfg,vtcfgYunsup Lee2-0/+10
2012-03-13opcodes cleanupYunsup Lee1-0/+0
2012-03-03add place holders for instructions to handle vector exceptionsYunsup Lee6-0/+0
2012-02-19fixed a bug in remu[w]Andrew Waterman2-2/+2
2012-02-15reimplement div[u][w]/rem[u][w]Andrew Waterman8-27/+39
2012-01-30fix divide by zero bugsYunsup Lee4-4/+4
2011-12-10fix utidx assign bug, make ut code execute fasterYunsup Lee1-1/+1
2011-11-11Changed MFTX to use rs1 for its sourceAndrew Waterman2-2/+2
2011-11-11Changed supervisor modeAndrew Waterman2-31/+20
2011-10-18fix vfYunsup Lee1-0/+1
2011-06-19temporary undoing of renamingAndrew Waterman272-0/+811
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman272-812/+0
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-1/+1
2011-06-11[xcc] instructions now set PC explicitlyAndrew Waterman14-18/+18
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman2-2/+2
2011-06-05[sim] fix writeback after ipi clearingAndrew Waterman1-0/+1
2011-06-04[sim] add ability to clear IPIsAndrew Waterman1-0/+3
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-1/+1
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman2-0/+12
2011-05-23[sim,xcc] add rdcycle/rdtime/rdinstretAndrew Waterman3-3/+3
2011-05-19[sim] more fp<->int fixesAndrew Waterman4-4/+4
2011-05-19[sim] more fp conversion bugs fixedAndrew Waterman2-2/+2
2011-05-18[sim] fixed fcvt rounding bugsAndrew Waterman8-8/+8
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee2-0/+9
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman3-1/+10
generated by cgit v1.1 at 2024-11-19 00:23:32 +0000