riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2015-02-08	Use xlen, not xprlen, to refer to x-register width	Andrew Waterman	1	-1/+1

2013-09-27	Use WRITE_RD/WRITE_FRD macros to write registers	Andrew Waterman	1	-1/+1

2011-06-19	temporary undoing of renaming	Andrew Waterman	1	-0/+1

2011-06-12	[sim] renamed to riscv-isa-run	Andrew Waterman	1	-1/+0

2011-04-16	[sim] removed undefined behavior for non-canonical inputs	Andrew Waterman	1	-1/+1

2011-01-18	[opcodes, sim, xcc] made *w insns illegal in RV32	Andrew Waterman	1	-2/+1
	now generic variants behave differently in RV32 and RV64.
2010-11-21	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	1	-1/+1

2010-09-22	[sim] fixed bug in which shift operands were reversed	Andrew Waterman	1	-1/+1

2010-09-20	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	1	-1/+1

2010-09-12	[sim] renamed sllv to sll (same for other shifts)	Andrew Waterman	1	-0/+2

2010-09-12	[xcc, sim] moved shamt field and renamed shifts	Andrew Waterman	1	-2/+0

2010-08-03	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	1	-1/+2
	All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr.
2010-07-28	[sim,xcc] Changed instruction format to RISC-V	Andrew Waterman	1	-1/+1
	Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes.
2010-07-18	Reorganized directory structure	Andrew Waterman	1	-0/+1
	Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/