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riscv-isa-sim.git
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eos18-bringup
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riscv
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remuw.h
Age
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Author
Files
Lines
2015-04-03
Support setting ISA/subsets with --isa flag
Andrew Waterman
1
-0
/
+1
2015-03-12
Update to new privileged spec
Andrew Waterman
1
-1
/
+1
2013-09-27
Use WRITE_RD/WRITE_FRD macros to write registers
Andrew Waterman
1
-2
/
+2
2012-02-19
fixed a bug in remu[w]
Andrew Waterman
1
-1
/
+1
2012-02-15
reimplement div[u][w]/rem[u][w]
Andrew Waterman
1
-3
/
+5
2012-01-30
fix divide by zero bugs
Yunsup Lee
1
-1
/
+1
2011-06-19
temporary undoing of renaming
Andrew Waterman
1
-0
/
+5
2011-06-12
[sim] renamed to riscv-isa-run
Andrew Waterman
1
-5
/
+0
2011-04-16
[sim] removed undefined behavior for non-canonical inputs
Andrew Waterman
1
-1
/
+1
2011-01-18
[opcodes, sim, xcc] made *w insns illegal in RV32
Andrew Waterman
1
-3
/
+4
2010-11-21
[sim] handle integer division overflow
Andrew Waterman
1
-2
/
+4
2010-11-21
[xcc, sim, pk, opcodes] new instruction encoding!
Andrew Waterman
1
-1
/
+1
2010-09-20
[xcc, sim] changed instruction format so imm12 subs for rs2
Andrew Waterman
1
-1
/
+1
2010-08-03
[pk,sim,xcc] Renamed instructions to RISC-V spec
Andrew Waterman
1
-0
/
+2