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author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 20:48:02 -0700 |
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committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-08-03 20:48:02 -0700 |
commit | 5ff63bcd7935cad840fd25844dfb590010bd2e12 (patch) | |
tree | 4efe8f8953dd229f1e3342e59108888296c99c46 /riscv/insns/remuw.h | |
parent | 864c3ef8ac39c27dec64adae6a1611755dfbada7 (diff) | |
download | riscv-isa-sim-5ff63bcd7935cad840fd25844dfb590010bd2e12.zip riscv-isa-sim-5ff63bcd7935cad840fd25844dfb590010bd2e12.tar.gz riscv-isa-sim-5ff63bcd7935cad840fd25844dfb590010bd2e12.tar.bz2 |
[pk,sim,xcc] Renamed instructions to RISC-V spec
All word-sized arithmetic operations are now postfixed with 'w',
and all double-word-sized arithmetic operations are no longer
prefixed with 'd'. mtc0/mfc0 are removed and replaced with
mfpcr/mtpcr/mwfpcr/mwtpcr.
Diffstat (limited to 'riscv/insns/remuw.h')
-rw-r--r-- | riscv/insns/remuw.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h new file mode 100644 index 0000000..d028488 --- /dev/null +++ b/riscv/insns/remuw.h @@ -0,0 +1,2 @@ +RC = sext32(uint32_t(RA) % uint32_t(RB)); + |