riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2021-10-14	Split 'P' to EXT_ZPN and friends (#830)	marcfedorow	1	-1/+1
	* Added ZMMUL extension * Splitted P-ext to its zeds * Typo fix
2015-04-03	Support setting ISA/subsets with --isa flag	Andrew Waterman	1	-0/+1
	Default is RV64IMAFDC. Can do things like --isa=RV32 (which implies IMAFDC) --isa=IM (which implies RV64) --isa=RV64IMAFDXhwacha
2015-03-12	Update to new privileged spec	Andrew Waterman	1	-1/+1
	Sorry, everyone.
2013-09-27	Use WRITE_RD/WRITE_FRD macros to write registers	Andrew Waterman	1	-1/+1

2011-06-19	temporary undoing of renaming	Andrew Waterman	1	-0/+2

2011-06-12	[sim] renamed to riscv-isa-run	Andrew Waterman	1	-2/+0

2011-01-18	[opcodes, sim, xcc] made *w insns illegal in RV32	Andrew Waterman	1	-1/+1
	now generic variants behave differently in RV32 and RV64.
2010-11-21	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	1	-1/+1

2010-09-20	[xcc, sim] changed instruction format so imm12 subs for rs2	Andrew Waterman	1	-1/+1

2010-08-03	[pk,sim,xcc] Renamed instructions to RISC-V spec	Andrew Waterman	1	-0/+2
	All word-sized arithmetic operations are now postfixed with 'w', and all double-word-sized arithmetic operations are no longer prefixed with 'd'. mtc0/mfc0 are removed and replaced with mfpcr/mtpcr/mwfpcr/mwtpcr.