index
:
riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
riscv
/
csrs.h
Age
Commit message (
Expand
)
Author
Files
Lines
2022-12-15
Split decode.h into public decode.h and private decode_macros.h
Jerry Zhao
1
-0
/
+2
2022-12-09
refactor: add tdata3_csr_t; preparation for CSR textra
YenHaoChen
1
-0
/
+8
2022-12-05
refactor: add custom CSR class, mevent_csr_t
YenHaoChen
1
-0
/
+7
2022-11-22
Add tinfo register.
Tim Newsome
1
-0
/
+8
2022-11-17
add support for zcmt
Weiwei Li
1
-0
/
+6
2022-10-04
Suppress most unused variable warnings
Andrew Waterman
1
-1
/
+1
2022-10-04
Fix remaining ignored-qualifiers warning
Andrew Waterman
1
-1
/
+1
2022-09-20
Merge pull request #1036 from plctlab/plct-sscofpmf-dev
Andrew Waterman
1
-0
/
+9
2022-08-11
Unify PMPCFGx behaviour with PMPADDRx where PMP is disabled (#1068)
Greg Chadwick
1
-0
/
+1
2022-08-09
add support for sscofpmf extension v0.5.2
Weiwei Li
1
-0
/
+9
2022-08-08
Merge pull request #1059 from plctlab/plct-stateen-fix
Andrew Waterman
1
-6
/
+0
2022-08-03
Add Sstc support. (#1057)
i2h2
1
-1
/
+16
2022-08-03
add stateen related check to frm/fflags and then apply to fcsr implicitly
Weiwei Li
1
-6
/
+0
2022-07-21
Merge pull request #1040 from plctlab/plct-priv-dev
Andrew Waterman
1
-7
/
+10
2022-07-21
add support for time/timeh/htimedelta/htimedeltah csrs
Weiwei Li
1
-0
/
+15
2022-07-21
modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_t
Weiwei Li
1
-14
/
+2
2022-07-18
Merge pull request #1041 from plctlab/plct-new-csrs
Andrew Waterman
1
-0
/
+1
2022-07-17
extract the progress of computing the inital value of mstatus into
Weiwei Li
1
-0
/
+1
2022-07-15
Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmp
Andrew Waterman
1
-0
/
+1
2022-07-13
Add proxy for accessing the low 32 bits of a 64-bit CSR
Scott Johnson
1
-0
/
+15
2022-07-13
Remove no-longer-needed mask from rv32_high_csr_t
Scott Johnson
1
-1
/
+0
2022-07-13
Remove unnecessary mask from rv32_high_csr_t constructor
Scott Johnson
1
-2
/
+2
2022-07-13
Add verify_permissions() for mseccfg_csr_t
YenHaoChen
1
-0
/
+1
2022-07-09
add smstateen check for fcsr, senvcfg, henvcfg
Weiwei Li
1
-0
/
+4
2022-07-09
add standalone class for fcsr and senvcfg csr
Weiwei Li
1
-0
/
+11
2022-07-09
add support for csrs of smstateen extensions
Weiwei Li
1
-0
/
+19
2022-07-07
modify mstatush_csr_t to general rv32_high_csr_t
Weiwei Li
1
-4
/
+6
2022-07-07
remove multi blank lines
Weiwei Li
1
-37
/
+0
2022-05-11
Change henvcfg csr to a henvcfg_csr_t
Ryan Buchner
1
-0
/
+14
2022-05-04
Implement the new csr mseccfg for ePMP as dummy
soberl@nvidia.com
1
-0
/
+16
2022-04-11
Merge pull request #944 from riscv-software-src/triggers
Scott Johnson
1
-4
/
+1
2022-04-04
Refactor misa masking
Mark Fedorov
1
-0
/
+1
2022-03-30
Move tdata2 into mcontrol_t
Tim Newsome
1
-4
/
+1
2022-03-16
Inline most implicit accesses to fflags/frm
Andrew Waterman
1
-1
/
+3
2022-03-15
Rewrite sstatus_csr_t::enabled() for higher performance
Andrew Waterman
1
-2
/
+5
2022-03-15
Give concrete types to fields of sstatus_proxy_csr_t
Andrew Waterman
1
-2
/
+2
2022-03-15
Give concrete types to fields of sstatus_csr_t
Andrew Waterman
1
-3
/
+4
2022-03-15
Allow sstatus_proxy_csr_t::read() to be inlined
Andrew Waterman
1
-2
/
+6
2022-03-15
Allow mstatus_csr_t::read() to be inlined
Andrew Waterman
1
-2
/
+6
2022-03-15
Allow vsstatus_csr_t::read() to be inlined
Andrew Waterman
1
-2
/
+6
2022-03-15
Move sstatus_proxy_csr_t defn below that of mstatus_csr_t
Andrew Waterman
1
-11
/
+11
2022-03-15
Fix perf regression from CSR refactoring (#949)
Andrew Waterman
1
-3
/
+13
2022-02-18
Split out MINSTRET and MCYCLE
Rupert Swarbrick
1
-4
/
+4
2022-02-18
Rename minstret CSR classes to something more general
Rupert Swarbrick
1
-7
/
+7
2021-11-13
Use enum to specify the 3 options for masking of intr CSRs
Scott Johnson
1
-2
/
+3
2021-11-13
Mask hideleg by mideleg
Scott Johnson
1
-0
/
+9
2021-11-02
Zbkx renames xperm.n and xperm.b as xperm4 and xperm8. (#846)
Markku-Juhani O. Saarinen
1
-2
/
+2
2021-10-15
Fix clang warning
Andrew Waterman
1
-1
/
+1
2021-10-06
Make vxsat into its own class
Scott Johnson
1
-0
/
+8
2021-10-06
Let each sstatus CSR determine extension enable
Scott Johnson
1
-0
/
+2
[next]