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AgeCommit message (Expand)AuthorFilesLines
2017-04-10WIP on FP encodingfp-encodingAndrew Waterman19-34/+31
2017-04-09WIP on FP encodingAndrew Waterman50-63/+89
2017-04-07Implement vectored interrupt proposalAndrew Waterman1-3/+5
2017-04-05Add --enable-misaligned option for misaligned ld/st supportAndrew Waterman4-4/+50
2017-03-31update encoding.h to get PMP updatesYunsup Lee1-5/+6
2017-03-31Update LICENSE copyright dateAndrew Waterman1-2/+2
2017-03-30fdt: move interrupt controller into its own nodeWesley W. Terpstra1-4/+7
2017-03-27Set badaddr=0 on illegal instruction trapsAndrew Waterman4-7/+7
2017-03-27On EBREAK, set badaddr to pcAndrew Waterman3-3/+3
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman4-13/+25
2017-03-24Default to 2 GiB of memoryAndrew Waterman1-1/+1
2017-03-23Require little-endian hostAndrew Waterman2-0/+14
2017-03-22riscv: replace rtc device with a real clint implementationWesley W. Terpstra8-55/+96
2017-03-21sim: declare cores as interrupt-controllers for clintWesley W. Terpstra1-0/+2
2017-03-21bootrom: set a0 to hartid and a1 to dtb before bootWesley W. Terpstra1-7/+7
2017-03-21configstring: rename variables to dtsWesley W. Terpstra3-12/+12
2017-03-21riscv: remove dependency on num_coresWesley W. Terpstra3-5/+1
2017-03-21bootrom: include compiled dtbWesley W. Terpstra1-1/+87
2017-03-21sim: create DTS instead of config stringWesley W. Terpstra1-26/+45
2017-03-21sim: define emulated CPU clock rate to be 1GHzWesley W. Terpstra1-0/+1
2017-03-21autoconf: put location of 'dtc' into config.hWesley W. Terpstra4-0/+52
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman3-8/+9
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman4-4/+44
2017-03-13Implement mstatus.TW, mstatus.TVM, and mstatus.TSRAndrew Waterman5-4/+12
2017-03-07Don't overload illegal instruction trap in interactive codeAndrew Waterman1-8/+10
2017-02-26Sv57 and Sv64 are not spec'd yetAndrew Waterman2-15/+11
2017-02-25New counter enable schemeAndrew Waterman3-31/+22
2017-02-20serialize simulator on wfiAndrew Waterman3-4/+5
2017-02-20Take M-mode interrupts over S-mode interruptsAndrew Waterman1-1/+2
2017-02-20permit MMIO loads to MSIP bitAndrew Waterman1-7/+18
2017-02-18Make HW setting of PTE A/D bits optional (by configure arg)Andrew Waterman4-2/+45
2017-02-18Spike uarch needs TLB flush after SPTBR writeAndrew Waterman2-1/+1
2017-02-15sfence.vm -> sfence.vmaAndrew Waterman3-4/+4
2017-02-08Encode VM type in sptbr, not mstatusAndrew Waterman6-137/+192
2017-02-07Merge pull request #83 from bacam/gdb-protocol-fixesTim Newsome1-5/+7
2017-02-02Fix interrupt delegation for coprocessorsAndrew Waterman4-19/+6
2017-02-01For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaNAndrew Waterman5-4/+13
2017-02-01Set xPIE=1 on xRETAndrew Waterman2-2/+2
2017-01-07Only allow SIP.SSIP to be toggled if the interrupt is delegatedAndrew Waterman1-1/+1
2017-01-07Make SIP.STIP read-onlyAndrew Waterman1-3/+4
2017-01-06Comply with GNU coding standards.David Craven1-2/+2
2016-12-30Only read exception flag in gdb register read/write. (#85)Brian Campbell1-2/+2
2016-12-21Fix gdb communication error (#82)Brian Campbell1-1/+1
2016-12-21Remove extra gdb protocol responses on register writesBrian Campbell1-2/+0
2016-12-21Fix gdb protocol register read of S0Brian Campbell1-3/+7
2016-12-16Use correct format codes for reg_t and size_tStefan O'Rear3-14/+15
2016-12-15Fix single stepping over faulting instructions. (#80)Tim Newsome1-0/+5
2016-12-12Reuse the ebreak constants in encoding.h.Tim Newsome1-9/+7
2016-12-01Added comments about the modified Duff's Device in execute.cc (#77)Andy Wright1-0/+37
2016-11-13Fix 32-bit host portability bugAndrew Waterman1-1/+1
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