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-rw-r--r--riscv/decode.h21
-rw-r--r--riscv/insns/c_fsd.h2
-rw-r--r--riscv/insns/c_fsdsp.h2
-rw-r--r--riscv/insns/c_fsw.h2
-rw-r--r--riscv/insns/c_fswsp.h2
-rw-r--r--riscv/insns/fmax_d.h4
-rw-r--r--riscv/insns/fmax_s.h4
-rw-r--r--riscv/insns/fmin_d.h4
-rw-r--r--riscv/insns/fmin_s.h4
-rw-r--r--riscv/insns/fmsub_d.h2
-rw-r--r--riscv/insns/fmsub_s.h2
-rw-r--r--riscv/insns/fmv_x_d.h2
-rw-r--r--riscv/insns/fmv_x_s.h2
-rw-r--r--riscv/insns/fnmadd_d.h2
-rw-r--r--riscv/insns/fnmadd_s.h2
-rw-r--r--riscv/insns/fnmsub_d.h2
-rw-r--r--riscv/insns/fnmsub_s.h2
-rw-r--r--riscv/insns/fsd.h2
-rw-r--r--riscv/insns/fsw.h2
19 files changed, 31 insertions, 34 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index e02cb74..c3487b1 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -18,16 +18,12 @@
#include "config.h"
#include "common.h"
#include "softfloat_types.h"
+#include "specialize.h"
#include <cinttypes>
typedef int64_t sreg_t;
typedef uint64_t reg_t;
-struct freg_t {
- uint64_t v;
- operator uint64_t() const { return v; }
-};
-
const int NXPR = 32;
const int NFPR = 32;
const int NCSR = 4096;
@@ -223,22 +219,23 @@ private:
#define invalid_pc(pc) ((pc) & 1)
/* Convenience wrappers to simplify softfloat code sequences */
+#define isBoxedF32(r) (((r) & 0xffffffff00000000) == 0xffffffff00000000)
+#define unboxF32(r) (isBoxedF32(r) ? (r) : defaultNaNF32UI)
+#define unboxF64(r) (r)
+struct freg_t { uint64_t v; };
inline float32_t f32(uint32_t v) { return { v }; }
-inline float32_t f32(freg_t r) { return { uint32_t(r) }; }
inline float64_t f64(uint64_t v) { return { v }; }
-inline float64_t f64(freg_t r) { return { uint64_t(r) }; }
+inline float32_t f32(freg_t r) { return f32(unboxF32(r.v)); }
+inline float64_t f64(freg_t r) { return f64(unboxF64(r.v)); }
inline freg_t freg(float32_t f) { return { ((decltype(freg_t::v))-1 << 32) | f.v }; }
inline freg_t freg(float64_t f) { return { f.v }; }
inline freg_t freg(freg_t f) { return f; }
#define F64_SIGN ((decltype(freg_t::v))1 << 63)
#define F32_SIGN ((decltype(freg_t::v))1 << 31)
-#define isBoxedF32(r) (((r) & 0x7fffffff00000000) == 0x7fffffff00000000)
-#define unboxF32(r) (isBoxedF32(r) ? (r) : defaultNaNF32UI)
-#define unboxF64(r) (r)
#define fsgnj32(a, b, n, x) \
- f32((unboxF32(a) & ~F32_SIGN) | ((((x) ? unboxF32(a) : (n) ? F32_SIGN : 0) ^ unboxF32(b)) & F32_SIGN))
+ f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
#define fsgnj64(a, b, n, x) \
- f64((unboxF64(a) & ~F64_SIGN) | ((((x) ? unboxF64(a) : (n) ? F64_SIGN : 0) ^ unboxF64(b)) & F64_SIGN))
+ f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
#define validate_csr(which, write) ({ \
if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \
diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index 84f1a7f..8743266 100644
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
require_extension('C');
require_extension('D');
require_fp;
-MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S);
+MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v);
diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h
index 5c5c680..f62f8ff 100644
--- a/riscv/insns/c_fsdsp.h
+++ b/riscv/insns/c_fsdsp.h
@@ -1,4 +1,4 @@
require_extension('C');
require_extension('D');
require_fp;
-MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2);
+MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v);
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 8923fef..b924a46 100644
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
if (xlen == 32) {
require_extension('F');
require_fp;
- MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S);
+ MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v);
} else { // c.sd
MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
}
diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index c13aa12..011de55 100644
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
if (xlen == 32) {
require_extension('F');
require_fp;
- MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2);
+ MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v);
} else { // c.sdsp
MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
}
diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index 9e75de0..9c8e5b3 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,6 +1,6 @@
require_extension('D');
require_fp;
-WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(uint64_t(FRS2)) ? FRS1 : FRS2);
-if ((isNaNF64UI(uint64_t(FRS1)) && isNaNF64UI(uint64_t(FRS2))) || softfloat_exceptionFlags)
+WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f64(defaultNaNF64UI));
set_fp_exceptions;
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index af9c507..2f570ea 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,6 +1,6 @@
require_extension('F');
require_fp;
-WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(uint32_t(FRS2)) ? FRS1 : FRS2);
-if ((isNaNF32UI(uint32_t(FRS1)) && isNaNF32UI(uint32_t(FRS2))) || softfloat_exceptionFlags)
+WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f32(defaultNaNF32UI));
set_fp_exceptions;
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index aa58bfd..cd40e15 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,6 +1,6 @@
require_extension('D');
require_fp;
-WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(uint64_t(FRS2)) ? FRS1 : FRS2);
-if ((isNaNF64UI(uint64_t(FRS1)) && isNaNF64UI(uint64_t(FRS2))) || softfloat_exceptionFlags)
+WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f64(defaultNaNF64UI));
set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 2739440..b813f45 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,6 +1,6 @@
require_extension('F');
require_fp;
-WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(uint32_t(FRS2)) ? FRS1 : FRS2);
-if ((isNaNF32UI(uint32_t(FRS1)) && isNaNF32UI(uint32_t(FRS2))) || softfloat_exceptionFlags)
+WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f32(defaultNaNF32UI));
set_fp_exceptions;
diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index 88f6c19..5b5bc0f 100644
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,5 +1,5 @@
require_extension('D');
require_fp;
softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)));
+WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
set_fp_exceptions;
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index 0eb4cdf..d46c887 100644
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,5 +1,5 @@
require_extension('F');
require_fp;
softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)));
+WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
set_fp_exceptions;
diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index b97d7f5..da8e72a 100644
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
require_extension('D');
require_rv64;
require_fp;
-WRITE_RD(FRS1);
+WRITE_RD(FRS1.v);
diff --git a/riscv/insns/fmv_x_s.h b/riscv/insns/fmv_x_s.h
index 5ccb8c1..b722479 100644
--- a/riscv/insns/fmv_x_s.h
+++ b/riscv/insns/fmv_x_s.h
@@ -1,3 +1,3 @@
require_extension('F');
require_fp;
-WRITE_RD(sext32(uint32_t(FRS1)));
+WRITE_RD(sext32(FRS1.v));
diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 245384c..e8dd743 100644
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,5 +1,5 @@
require_extension('D');
require_fp;
softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)));
+WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 82b5dad..1c2996e 100644
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,5 +1,5 @@
require_extension('F');
require_fp;
softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)));
+WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index e14a673..c29a0b9 100644
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,5 +1,5 @@
require_extension('D');
require_fp;
softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3)));
+WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3)));
set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index e1448ce..4c61fc7 100644
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,5 +1,5 @@
require_extension('F');
require_fp;
softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)));
+WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
set_fp_exceptions;
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 63cc8e5..679cc95 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
require_extension('D');
require_fp;
-MMU.store_uint64(RS1 + insn.s_imm(), FRS2);
+MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v);
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 3135e9b..42fc683 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
require_extension('F');
require_fp;
-MMU.store_uint32(RS1 + insn.s_imm(), FRS2);
+MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v);
generated by cgit v1.1 at 2025-01-12 00:59:53 +0000