diff options
| author | Tim Newsome <tim@sifive.com> | 2016-05-01 12:05:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 990c6c48098e83584edf5282d119187abae04a4d (patch) | |
| tree | d2ba581b281dce0c329822f98cc7c21faf868323 /tests/testlib.py | |
| parent | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff) | |
| download | riscv-isa-sim-990c6c48098e83584edf5282d119187abae04a4d.zip riscv-isa-sim-990c6c48098e83584edf5282d119187abae04a4d.tar.gz riscv-isa-sim-990c6c48098e83584edf5282d119187abae04a4d.tar.bz2 | |
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'tests/testlib.py')
0 files changed, 0 insertions, 0 deletions