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| author | Andrew Waterman <andrew@sifive.com> | 2024-01-11 17:24:51 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-11 17:24:51 -0800 |
| commit | f80fc52e8842d3a5270b787a0fc57028edca5dab (patch) | |
| tree | fbf9a8940073159702e710c17762f5b4570a347f /riscv | |
| parent | 8f045178d0c0319010cc5363ab69181e7ed318b9 (diff) | |
| parent | f8b2e39258d6de74652203a5ca357bb918e3ed53 (diff) | |
| download | riscv-isa-sim-f80fc52e8842d3a5270b787a0fc57028edca5dab.zip riscv-isa-sim-f80fc52e8842d3a5270b787a0fc57028edca5dab.tar.gz riscv-isa-sim-f80fc52e8842d3a5270b787a0fc57028edca5dab.tar.bz2 | |
Merge pull request #1563 from demin-han/master
Refactor put_csr to direct write
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/mret.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/mret.h b/riscv/insns/mret.h index f5f86a2..a6fcd13 100644 --- a/riscv/insns/mret.h +++ b/riscv/insns/mret.h @@ -9,5 +9,5 @@ s = set_field(s, MSTATUS_MIE, get_field(s, MSTATUS_MPIE)); s = set_field(s, MSTATUS_MPIE, 1); s = set_field(s, MSTATUS_MPP, p->extension_enabled('U') ? PRV_U : PRV_M); s = set_field(s, MSTATUS_MPV, 0); -p->put_csr(CSR_MSTATUS, s); +STATE.mstatus->write(s); p->set_privilege(prev_prv, prev_virt); |