diff options
author | YenHaoChen <howard25336284@gmail.com> | 2023-07-17 12:04:56 +0800 |
---|---|---|
committer | YenHaoChen <howard25336284@gmail.com> | 2023-07-25 08:41:13 +0800 |
commit | f6e7338b26f1508bdcc823ff1920427bf72e95ae (patch) | |
tree | eeb14bed1730b165a21c9ac9f373e89645c6d115 /riscv | |
parent | 432c9ee97613ec73bbb10591f0cef9c1c93b4284 (diff) | |
download | riscv-isa-sim-f6e7338b26f1508bdcc823ff1920427bf72e95ae.zip riscv-isa-sim-f6e7338b26f1508bdcc823ff1920427bf72e95ae.tar.gz riscv-isa-sim-f6e7338b26f1508bdcc823ff1920427bf72e95ae.tar.bz2 |
legalize menvcfg.CBIE
The value 2 of menvcfg.CBIE is reserved. This commit legalizes it to 0
by adding a specialized class envcfg_csr_t.
Reference: https://github.com/riscv/riscv-CMOs/issues/65
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/csrs.cc | 13 | ||||
-rw-r--r-- | riscv/csrs.h | 7 | ||||
-rw-r--r-- | riscv/processor.cc | 2 |
3 files changed, 21 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 7ea07d1..a895b6c 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -901,6 +901,19 @@ bool masked_csr_t::unlogged_write(const reg_t val) noexcept { return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } +envcfg_csr_t::envcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, + const reg_t init): + masked_csr_t(proc, addr, mask, init) { + // In unlogged_write() we WARLize this field for all three of [msh]envcfg + assert(MENVCFG_CBIE == SENVCFG_CBIE && MENVCFG_CBIE == HENVCFG_CBIE); +} + +bool envcfg_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t cbie_reserved = 2; // Reserved value of xenvcfg.CBIE + const reg_t adjusted_val = get_field(val, MENVCFG_CBIE) != cbie_reserved ? val : set_field(val, MENVCFG_CBIE, 0); + return masked_csr_t::unlogged_write(adjusted_val); +} + // implement class henvcfg_csr_t henvcfg_csr_t::henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg): masked_csr_t(proc, addr, mask, init), diff --git a/riscv/csrs.h b/riscv/csrs.h index 07d6d82..f152802 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -458,6 +458,13 @@ class masked_csr_t: public basic_csr_t { const reg_t mask; }; +class envcfg_csr_t: public masked_csr_t { + public: + envcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + // henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 // henvcfg.stce is read_only 0 when menvcfg.stce = 0 // henvcfg.hade is read_only 0 when menvcfg.hade = 0 diff --git a/riscv/processor.cc b/riscv/processor.cc index e81375a..2f458bf 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -445,7 +445,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0) | (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0); const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0); - menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init); + menvcfg = std::make_shared<envcfg_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init); if (xlen == 32) { csrmap[CSR_MENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_MENVCFG, menvcfg); csrmap[CSR_MENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MENVCFGH, menvcfg); |