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| author | Andrew Waterman <andrew@sifive.com> | 2020-04-20 03:44:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-04-20 03:44:16 -0700 |
| commit | d1b6eb11137d5fd23156bb32fe42eaec30b558c5 (patch) | |
| tree | 4d3f1cba3d2ae4f160c6236c1c5f42fb37dbd269 /riscv | |
| parent | ecb15182b55c03bbe7b20a8f7fdc59b6878586e7 (diff) | |
| download | riscv-isa-sim-d1b6eb11137d5fd23156bb32fe42eaec30b558c5.zip riscv-isa-sim-d1b6eb11137d5fd23156bb32fe42eaec30b558c5.tar.gz riscv-isa-sim-d1b6eb11137d5fd23156bb32fe42eaec30b558c5.tar.bz2 | |
Move vxrm/vxsat from fcsr to vcsr
See https://github.com/riscv/riscv-v-spec/commit/951b64fb10f9489ec98a27d3ef1a09e78c1037bf
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 8 | ||||
| -rw-r--r-- | riscv/encoding.h | 2 | ||||
| -rw-r--r-- | riscv/processor.cc | 22 |
3 files changed, 16 insertions, 16 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index cc7cf56..e1cc414 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -34,11 +34,11 @@ const int NCSR = 4096; #define X_RA 1 #define X_SP 2 -#define FSR_VXRM_SHIFT 9 -#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) -#define FSR_VXSAT_SHIFT 8 -#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) #define FP_RD_NE 0 #define FP_RD_0 1 diff --git a/riscv/encoding.h b/riscv/encoding.h index 371457f..2729f23 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1569,6 +1569,7 @@ #define CSR_VSTART 0x8 #define CSR_VXSAT 0x9 #define CSR_VXRM 0xa +#define CSR_VCSR 0xf #define CSR_USCRATCH 0x40 #define CSR_UEPC 0x41 #define CSR_UCAUSE 0x42 @@ -2521,6 +2522,7 @@ DECLARE_CSR(utvec, CSR_UTVEC) DECLARE_CSR(vstart, CSR_VSTART) DECLARE_CSR(vxsat, CSR_VXSAT) DECLARE_CSR(vxrm, CSR_VXRM) +DECLARE_CSR(vcsr, CSR_VCSR) DECLARE_CSR(uscratch, CSR_USCRATCH) DECLARE_CSR(uepc, CSR_UEPC) DECLARE_CSR(ucause, CSR_UCAUSE) diff --git a/riscv/processor.cc b/riscv/processor.cc index 4810297..597426f 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -607,10 +607,11 @@ void processor_t::set_csr(int which, reg_t val) dirty_fp_state; state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT; state.frm = (val & FSR_RD) >> FSR_RD_SHIFT; - if (supports_extension('V')) { - VU.vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; - VU.vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; - } + break; + case CSR_VCSR: + dirty_vs_state; + VU.vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; + VU.vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; break; case CSR_MSTATUS: { if ((val ^ state.mstatus) & @@ -873,15 +874,12 @@ reg_t processor_t::get_csr(int which) break; return state.frm; case CSR_FCSR: - {require_fp; - if (!supports_extension('F')) + require_fp; + return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT); + case CSR_VCSR: + if (!supports_extension('V')) break; - uint32_t shared_flags = 0; - if (supports_extension('V')) - shared_flags = (VU.vxrm << FSR_VXRM_SHIFT) | (VU.vxsat << FSR_VXSAT_SHIFT); - return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT) | - shared_flags; - } + return (VU.vxsat << VCSR_VXSAT_SHIFT) | (VU.vxrm << VCSR_VXRM_SHIFT); case CSR_INSTRET: case CSR_CYCLE: if (ctr_ok) |