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author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-03-15 16:48:16 -0700 |
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committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-03-15 16:48:16 -0700 |
commit | a0765388661018f059f74379b5497cf1607f4846 (patch) | |
tree | 6f3aadbd7c884fd37ce6a6f27ab554a6b167a91a /riscv | |
parent | 466b679dcf3a3469d7f394ffdda0ea6f326dfb3c (diff) | |
download | riscv-isa-sim-a0765388661018f059f74379b5497cf1607f4846.zip riscv-isa-sim-a0765388661018f059f74379b5497cf1607f4846.tar.gz riscv-isa-sim-a0765388661018f059f74379b5497cf1607f4846.tar.bz2 |
speed up compilation a bit
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/processor.cc | 1 | ||||
-rw-r--r-- | riscv/processor.h | 3 |
2 files changed, 2 insertions, 2 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index e931c6b..39848b4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -32,6 +32,7 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) processor_t::~processor_t() { + delete disassembler; } void state_t::reset() diff --git a/riscv/processor.h b/riscv/processor.h index 9e52d3d..e2847fa 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -5,7 +5,6 @@ #include "decode.h" #include "config.h" #include <cstring> -#include <memory> #include <vector> class processor_t; @@ -80,7 +79,7 @@ private: sim_t* sim; mmu_t* mmu; // main memory is always accessed via the mmu extension_t* ext; - std::unique_ptr<disassembler_t> disassembler; + disassembler_t* disassembler; state_t state; uint32_t id; bool run; // !reset |