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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-31 20:38:10 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 22:34:09 +0800 |
commit | 6b28c78b2cfdf562934fd1d65812cc8707f2cc41 (patch) | |
tree | 6fddc4b3eb56e057a2e2adfe267b7ad9831425f9 /riscv | |
parent | 7383118078a98112ca4036919e6654d8171d2274 (diff) | |
download | riscv-isa-sim-6b28c78b2cfdf562934fd1d65812cc8707f2cc41.zip riscv-isa-sim-6b28c78b2cfdf562934fd1d65812cc8707f2cc41.tar.gz riscv-isa-sim-6b28c78b2cfdf562934fd1d65812cc8707f2cc41.tar.bz2 |
Add #ifdef RISCV_ENABLE_COMMITLOG for commitlog related code
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index 7cb16dd..cc0d4c3 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -172,8 +172,10 @@ inline void processor_t::update_histogram(reg_t pc) // function calls. static inline reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) { +#ifdef RISCV_ENABLE_COMMITLOG commit_log_reset(p); commit_log_stash_privilege(p); +#endif reg_t npc; try { |