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| author | liangsen <liangsen20z@ict.ac.cn> | 2024-01-10 11:29:41 +0800 |
|---|---|---|
| committer | Liang Sen <liangsen20z@ict.ac.cn> | 2024-02-11 20:10:34 +0800 |
| commit | 410276cf1f09829c1bef322ab6ebc97f29b90dab (patch) | |
| tree | aa47d3aa877d8bbb18c68d6a7816acd83dba2037 /riscv | |
| parent | 3a53c80ade3336b1d46c9db3a6c6be8311c32cc5 (diff) | |
| download | riscv-isa-sim-410276cf1f09829c1bef322ab6ebc97f29b90dab.zip riscv-isa-sim-410276cf1f09829c1bef322ab6ebc97f29b90dab.tar.gz riscv-isa-sim-410276cf1f09829c1bef322ab6ebc97f29b90dab.tar.bz2 | |
Support run until paddr changed to a certain value
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/interactive.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index d9fb39b..8dc4828 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -721,7 +721,7 @@ void sim_t::interactive_until(const std::string& cmd, const std::vector<std::str if (args.size() < 3) throw trap_interactive(); - if (args.size() == 3) + if (args.size() == 4 || (args[0] == "pc" && args.size() == 3)) //dont check mem with arg len = 3 get_core(args[1]); // make sure that argument is a valid core number char *end; @@ -732,7 +732,9 @@ void sim_t::interactive_until(const std::string& cmd, const std::vector<std::str throw trap_interactive(); // mask bits above max_xlen - int max_xlen = procs[strtol(args[1].c_str(),NULL,10)]->get_isa().get_max_xlen(); + bool until_mem_paddr = args[0] == "mem" && args.size() == 3; + size_t procnum = until_mem_paddr ? 0 : strtol(args[1].c_str(), NULL, 10); + int max_xlen = procs[procnum]->get_isa().get_max_xlen(); if (max_xlen == 32) val &= 0xFFFFFFFF; std::vector<std::string> args2; |