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authorAtul Khare <atulkhare@rivosinc.com>2023-07-24 17:56:38 -0700
committerAtul Khare <atulkhare@rivosinc.com>2023-07-26 09:10:27 -0700
commit1c91fd56ba54bf62c67fea94b80726008895a57a (patch)
treea7171bec8077670c1bc2639e0a0ee44f74bb7f5c /riscv
parent60c08b1ea5e3d96a97c235db87d472a7cfb2611b (diff)
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Regenerate encoding.h
Diffstat (limited to 'riscv')
-rw-r--r--riscv/encoding.h57
1 files changed, 40 insertions, 17 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h
index 9666774..f1defd4 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -4,7 +4,7 @@
/*
* This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (be53d24)
+ * https://github.com/riscv/riscv-opcodes (6790b30)
*/
#ifndef RISCV_CSR_ENCODING_H
@@ -172,6 +172,7 @@
#define MSTATEEN0_FCSR 0x00000002
#define MSTATEEN0_JVT 0x00000004
#define MSTATEEN0_HCONTEXT 0x0200000000000000
+#define MSTATEEN0_CD 0x0100000000000000
#define MSTATEEN0_HENVCFG 0x4000000000000000
#define MSTATEEN_HSTATEEN 0x8000000000000000
@@ -205,6 +206,18 @@
#define HENVCFGH_PBMTE 0x40000000
#define HENVCFGH_STCE 0x80000000
+#define SISELECT_SMCDELEG_START 0x40
+#define SISELECT_SMCDELEG_UNUSED 0x41
+#define SISELECT_SMCDELEG_INSTRET 0x42
+#define SISELECT_SMCDELEG_INSTRETCFG 0x42
+/*
+ * ?iselect values for hpmcounters4..31 and hpmevent4..31
+ * can easily computed, and were elided for brevity.
+ */
+#define SISELECT_SMCDELEG_HPMCOUNTER_3 0x43
+#define SISELECT_SMCDELEG_HPMEVENT_3 0x43
+#define SISELECT_SMCDELEG_END 0x5f
+
#define HSTATEEN0_CS 0x00000001
#define HSTATEEN0_FCSR 0x00000002
#define HSTATEEN0_JVT 0x00000004
@@ -2477,10 +2490,10 @@
#define MASK_VMADD_VV 0xfc00707f
#define MATCH_VMADD_VX 0xa4006057
#define MASK_VMADD_VX 0xfc00707f
-#define MATCH_VMAND_MM 0x64002057
-#define MASK_VMAND_MM 0xfc00707f
-#define MATCH_VMANDN_MM 0x60002057
-#define MASK_VMANDN_MM 0xfc00707f
+#define MATCH_VMAND_MM 0x66002057
+#define MASK_VMAND_MM 0xfe00707f
+#define MATCH_VMANDN_MM 0x62002057
+#define MASK_VMANDN_MM 0xfe00707f
#define MATCH_VMAX_VV 0x1c000057
#define MASK_VMAX_VV 0xfc00707f
#define MATCH_VMAX_VX 0x1c004057
@@ -2523,14 +2536,14 @@
#define MASK_VMINU_VV 0xfc00707f
#define MATCH_VMINU_VX 0x10004057
#define MASK_VMINU_VX 0xfc00707f
-#define MATCH_VMNAND_MM 0x74002057
-#define MASK_VMNAND_MM 0xfc00707f
-#define MATCH_VMNOR_MM 0x78002057
-#define MASK_VMNOR_MM 0xfc00707f
-#define MATCH_VMOR_MM 0x68002057
-#define MASK_VMOR_MM 0xfc00707f
-#define MATCH_VMORN_MM 0x70002057
-#define MASK_VMORN_MM 0xfc00707f
+#define MATCH_VMNAND_MM 0x76002057
+#define MASK_VMNAND_MM 0xfe00707f
+#define MATCH_VMNOR_MM 0x7a002057
+#define MASK_VMNOR_MM 0xfe00707f
+#define MATCH_VMOR_MM 0x6a002057
+#define MASK_VMOR_MM 0xfe00707f
+#define MATCH_VMORN_MM 0x72002057
+#define MASK_VMORN_MM 0xfe00707f
#define MATCH_VMSBC_VV 0x4e000057
#define MASK_VMSBC_VV 0xfe00707f
#define MATCH_VMSBC_VVM 0x4c000057
@@ -2619,10 +2632,10 @@
#define MASK_VMV_V_X 0xfff0707f
#define MATCH_VMV_X_S 0x42002057
#define MASK_VMV_X_S 0xfe0ff07f
-#define MATCH_VMXNOR_MM 0x7c002057
-#define MASK_VMXNOR_MM 0xfc00707f
-#define MATCH_VMXOR_MM 0x6c002057
-#define MASK_VMXOR_MM 0xfc00707f
+#define MATCH_VMXNOR_MM 0x7e002057
+#define MASK_VMXNOR_MM 0xfe00707f
+#define MATCH_VMXOR_MM 0x6e002057
+#define MASK_VMXOR_MM 0xfe00707f
#define MATCH_VNCLIP_WI 0xbc003057
#define MASK_VNCLIP_WI 0xfc00707f
#define MATCH_VNCLIP_WV 0xbc000057
@@ -3051,6 +3064,7 @@
#define CSR_SSTATEEN1 0x10d
#define CSR_SSTATEEN2 0x10e
#define CSR_SSTATEEN3 0x10f
+#define CSR_SCOUNTINHIBIT 0x120
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
@@ -3280,6 +3294,8 @@
#define CSR_MHPMCOUNTER29 0xb1d
#define CSR_MHPMCOUNTER30 0xb1e
#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MCYCLECFG 0x321
+#define CSR_MINSTRETCFG 0x322
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
@@ -3375,6 +3391,8 @@
#define CSR_MSTATEEN2H 0x31e
#define CSR_MSTATEEN3H 0x31f
#define CSR_MIPH 0x354
+#define CSR_MCYCLECFGH 0x721
+#define CSR_MINSTRETCFGH 0x722
#define CSR_MHPMEVENT3H 0x723
#define CSR_MHPMEVENT4H 0x724
#define CSR_MHPMEVENT5H 0x725
@@ -4933,6 +4951,7 @@ DECLARE_CSR(sstateen0, CSR_SSTATEEN0)
DECLARE_CSR(sstateen1, CSR_SSTATEEN1)
DECLARE_CSR(sstateen2, CSR_SSTATEEN2)
DECLARE_CSR(sstateen3, CSR_SSTATEEN3)
+DECLARE_CSR(scountinhibit, CSR_SCOUNTINHIBIT)
DECLARE_CSR(sscratch, CSR_SSCRATCH)
DECLARE_CSR(sepc, CSR_SEPC)
DECLARE_CSR(scause, CSR_SCAUSE)
@@ -5162,6 +5181,8 @@ DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG)
+DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG)
DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
@@ -5257,6 +5278,8 @@ DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H)
DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H)
DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H)
DECLARE_CSR(miph, CSR_MIPH)
+DECLARE_CSR(mcyclecfgh, CSR_MCYCLECFGH)
+DECLARE_CSR(minstretcfgh, CSR_MINSTRETCFGH)
DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H)
DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H)
DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H)