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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 21:03:23 -0800 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 21:03:23 -0800 |
commit | 15ca044738d478f427300d211fe50e9a1b1b5ac6 (patch) | |
tree | 50f2cfd6ac5c5e1f3496c3786daeb87cd6d54381 /riscv | |
parent | d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be (diff) | |
download | riscv-isa-sim-15ca044738d478f427300d211fe50e9a1b1b5ac6.zip riscv-isa-sim-15ca044738d478f427300d211fe50e9a1b1b5ac6.tar.gz riscv-isa-sim-15ca044738d478f427300d211fe50e9a1b1b5ac6.tar.bz2 |
add accelerator disabled cause
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/pcr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/pcr.h b/riscv/pcr.h index b90884b..6c6d986 100644 --- a/riscv/pcr.h +++ b/riscv/pcr.h @@ -59,6 +59,7 @@ #define CAUSE_MISALIGNED_STORE 9 #define CAUSE_FAULT_LOAD 10 #define CAUSE_FAULT_STORE 11 +#define CAUSE_ACCELERATOR_DISABLED 12 // page table entry (PTE) fields #define PTE_V 0x001 // Entry is a page Table descriptor |