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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-02-07 17:05:21 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-02 12:15:25 -0800 |
| commit | 0d5bd9e810db2f2eafaed3de472ac1130501fd41 (patch) | |
| tree | 4ddf8797102d2fa3bdb788c113d22382ecc0202a /riscv | |
| parent | df37931703b2dbacb69227e2bbe0eb51f38ad87b (diff) | |
| download | riscv-isa-sim-0d5bd9e810db2f2eafaed3de472ac1130501fd41.zip riscv-isa-sim-0d5bd9e810db2f2eafaed3de472ac1130501fd41.tar.gz riscv-isa-sim-0d5bd9e810db2f2eafaed3de472ac1130501fd41.tar.bz2 | |
Set default RV32 RAM size to 4 GiB - 256 MiB
This allows, by default, 256 MiB of addressable I/O space.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/sim.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 67b655e..69d5e19 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -30,11 +30,11 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, size_t memsz0 = (size_t)mem_mb << 20; size_t quantum = 1L << 20; if (memsz0 == 0) - memsz0 = 1L << (sizeof(size_t) == 8 ? 32 : 30); + memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20; memsz = memsz0; while ((mem = (char*)calloc(1, memsz)) == NULL) - memsz = memsz*10/11/quantum*quantum; + memsz = (size_t)(memsz*0.9)/quantum*quantum; if (memsz != memsz0) fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n", |