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| author | YenHaoChen <howard25336284@gmail.com> | 2022-12-30 11:28:19 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-01-04 08:07:52 +0800 |
| commit | 9f4a93dbf92b5a9e475b3f18335a40bb3f122030 (patch) | |
| tree | 94a9fd13e6f3e1a6c6929c0f4865e0c8b83f2d1a /riscv/triggers.cc | |
| parent | 007199efdce2b52650fac5822e2dd2351a0a16b9 (diff) | |
| download | riscv-isa-sim-9f4a93dbf92b5a9e475b3f18335a40bb3f122030.zip riscv-isa-sim-9f4a93dbf92b5a9e475b3f18335a40bb3f122030.tar.gz riscv-isa-sim-9f4a93dbf92b5a9e475b3f18335a40bb3f122030.tar.bz2 | |
triggers: refactor: add bool etrigger_t::simple_match()
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 60e9ea2..07d1484 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -370,13 +370,18 @@ std::optional<match_result_t> etrigger_t::detect_trap_match(processor_t * const bool interrupt = (t.cause() & ((reg_t)1 << (xlen - 1))) != 0; reg_t bit = t.cause() & ~((reg_t)1 << (xlen - 1)); assert(bit < xlen); - if (!interrupt && ((tdata2 >> bit) & 1)) { + if (simple_match(interrupt, bit)) { hit = true; return match_result_t(TIMING_AFTER, action); } return std::nullopt; } +bool etrigger_t::simple_match(bool interrupt, reg_t bit) const +{ + return !interrupt && ((tdata2 >> bit) & 1); +} + module_t::module_t(unsigned count) : triggers(count) { for (unsigned i = 0; i < count; i++) { triggers[i] = new disabled_trigger_t(); |