diff options
| author | YenHaoChen <howard25336284@gmail.com> | 2022-12-30 11:22:20 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2023-01-04 08:07:52 +0800 |
| commit | 007199efdce2b52650fac5822e2dd2351a0a16b9 (patch) | |
| tree | 692bc95b2915bcd89b4bb0aa54633a9d8fb57684 /riscv/triggers.cc | |
| parent | 85f7869bf58a4d9b3d4a09f9f312c2deb7b3c81a (diff) | |
| download | riscv-isa-sim-007199efdce2b52650fac5822e2dd2351a0a16b9.zip riscv-isa-sim-007199efdce2b52650fac5822e2dd2351a0a16b9.tar.gz riscv-isa-sim-007199efdce2b52650fac5822e2dd2351a0a16b9.tar.bz2 | |
triggers: refactor: add bool itrigger_t::simple_match()
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 0ff36e8..60e9ea2 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -319,13 +319,18 @@ std::optional<match_result_t> itrigger_t::detect_trap_match(processor_t * const bool interrupt = (t.cause() & ((reg_t)1 << (xlen - 1))) != 0; reg_t bit = t.cause() & ~((reg_t)1 << (xlen - 1)); assert(bit < xlen); - if (interrupt && ((bit == 0 && nmi) || ((tdata2 >> bit) & 1))) { // Assume NMI's exception code is 0 + if (simple_match(interrupt, bit)) { hit = true; return match_result_t(TIMING_AFTER, action); } return std::nullopt; } +bool itrigger_t::simple_match(bool interrupt, reg_t bit) const +{ + return interrupt && ((bit == 0 && nmi) || ((tdata2 >> bit) & 1)); // Assume NMI's exception code is 0 +} + reg_t etrigger_t::tdata1_read(const processor_t * const proc) const noexcept { auto xlen = proc->get_xlen(); |