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| author | Tim Newsome <tim@sifive.com> | 2022-11-15 09:47:26 -0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-11-29 07:47:54 +0800 |
| commit | 3aec432e12c4d306326d59adbe26cd7b88c686da (patch) | |
| tree | e934d01f733c1566fd3d7991ef1d7d18e61baed0 /riscv/triggers.cc | |
| parent | 9b7f1a8642cfcf78e6555c528342f58c7b862119 (diff) | |
| download | riscv-isa-sim-3aec432e12c4d306326d59adbe26cd7b88c686da.zip riscv-isa-sim-3aec432e12c4d306326d59adbe26cd7b88c686da.tar.gz riscv-isa-sim-3aec432e12c4d306326d59adbe26cd7b88c686da.tar.bz2 | |
triggers: rename store
store() -> get_store()
store_bit -> store
Diffstat (limited to 'riscv/triggers.cc')
| -rw-r--r-- | riscv/triggers.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 94b1fdd..6c03c9e 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -33,7 +33,7 @@ reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { v = set_field(v, MCONTROL_S, s); v = set_field(v, MCONTROL_U, u); v = set_field(v, MCONTROL_EXECUTE, execute); - v = set_field(v, MCONTROL_STORE, store_bit); + v = set_field(v, MCONTROL_STORE, store); v = set_field(v, MCONTROL_LOAD, load); return v; } @@ -67,7 +67,7 @@ bool mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val) noexcep s = get_field(val, MCONTROL_S); u = get_field(val, MCONTROL_U); execute = get_field(val, MCONTROL_EXECUTE); - store_bit = get_field(val, MCONTROL_STORE); + store = get_field(val, MCONTROL_STORE); load = get_field(val, MCONTROL_LOAD); // Assume we're here because of csrw. if (execute) @@ -105,7 +105,7 @@ bool mcontrol_t::simple_match(unsigned xlen, reg_t value) const { match_result_t mcontrol_t::memory_access_match(processor_t * const proc, operation_t operation, reg_t address, std::optional<reg_t> data) { state_t * const state = proc->get_state(); if ((operation == triggers::OPERATION_EXECUTE && !execute) || - (operation == triggers::OPERATION_STORE && !store_bit) || + (operation == triggers::OPERATION_STORE && !store) || (operation == triggers::OPERATION_LOAD && !load) || (state->prv == PRV_M && !m) || (state->prv == PRV_S && !s) || |