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authorAndrew Waterman <andrew@sifive.com>2022-10-17 13:51:59 -0700
committerAndrew Waterman <andrew@sifive.com>2022-10-17 13:51:59 -0700
commit68aeeb5500521ff52c216862f9a653b64191f3ad (patch)
tree407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/sim.cc
parent191634d2854dfed448fc323195f9b65c305e2d77 (diff)
parent03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff)
downloadriscv-isa-sim-plic_uart_v1.zip
riscv-isa-sim-plic_uart_v1.tar.gz
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Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r--riscv/sim.cc7
1 files changed, 2 insertions, 5 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc
index e909009..5ce7d21 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -225,6 +225,7 @@ int sim_t::run()
{
host = context_t::current();
target.init(sim_thread_main, this);
+ htif_t::set_expected_xlen(isa.get_max_xlen());
return htif_t::run();
}
@@ -326,7 +327,7 @@ void sim_t::make_dtb()
std::pair<reg_t, reg_t> initrd_bounds = cfg->initrd_bounds();
dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ,
initrd_bounds.first, initrd_bounds.second,
- cfg->bootargs(), procs, mems);
+ cfg->bootargs(), cfg->pmpregions, procs, mems);
dtb = dts_compile(dts);
}
@@ -449,11 +450,7 @@ void sim_t::set_target_endianness(memif_endianness_t endianness)
memif_endianness_t sim_t::get_target_endianness() const
{
-#ifdef RISCV_ENABLE_DUAL_ENDIAN
return debug_mmu->is_target_big_endian()? memif_endianness_big : memif_endianness_little;
-#else
- return memif_endianness_little;
-#endif
}
void sim_t::proc_reset(unsigned id)