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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 19:39:30 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-09 00:02:20 -0700 |
| commit | ef5950ea11c4ef97bbe9a025a70950f754b38959 (patch) | |
| tree | 8020233d5f3fb422e7c33348bfb79ea8aac365ec /riscv/riscv.ac | |
| parent | aa1392d063cf52685f33e5c8d2a6b42a04ede948 (diff) | |
| download | riscv-isa-sim-ef5950ea11c4ef97bbe9a025a70950f754b38959.zip riscv-isa-sim-ef5950ea11c4ef97bbe9a025a70950f754b38959.tar.gz riscv-isa-sim-ef5950ea11c4ef97bbe9a025a70950f754b38959.tar.bz2 | |
rvv: handle middle value of vslidedown.vx
The spec doesn't limit the range of middle value.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/riscv.ac')
0 files changed, 0 insertions, 0 deletions