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| author | Andrew Waterman <andrew@sifive.com> | 2026-02-13 15:30:01 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2026-02-13 15:47:33 -0800 |
| commit | a1cf82541b565c88f87a270f191aaaac5f03978f (patch) | |
| tree | 63810401b76bfec4dc5863527d58c65b55c0918b /riscv/processor.h | |
| parent | eb6586e3dea4a622bcdd4d518b25f8202b90eb40 (diff) | |
| download | riscv-isa-sim-fetch.zip riscv-isa-sim-fetch.tar.gz riscv-isa-sim-fetch.tar.bz2 | |
Speed up I$ refillfetch
Leverage the vastly common case that instructions are only 2 or 4 bytes,
hit in the TLB, and do not span a page boundary.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index cb05210..db7b8ba 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -404,7 +404,17 @@ private: void parse_priv_string(const char*); void register_base_instructions(); - insn_func_t decode_insn(insn_t insn); + + insn_func_t ALWAYS_INLINE decode_insn(insn_t insn) + { + const auto& pool = opcode_map[insn.bits() % std::size(opcode_map)]; + + for (auto p = pool.begin(); ; ++p) { + if ((insn.bits() & p->mask) == p->match) { + return p->func; + } + } + } // Track repeated executions for processor_t::disasm() uint64_t last_pc, last_bits, executions; |
