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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-02-20 15:16:53 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-03-06 12:07:03 -0600 |
| commit | 4a97a05a6e806f7abcb6cd30685093aa5b9331a9 (patch) | |
| tree | 8454d198cbb618ab3e120871f48b7c9c0503e06b /riscv/mmu.cc | |
| parent | 58aa702359ec56f0b26a3f10a2617a58c9818451 (diff) | |
| download | riscv-isa-sim-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.zip riscv-isa-sim-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.tar.gz riscv-isa-sim-4a97a05a6e806f7abcb6cd30685093aa5b9331a9.tar.bz2 | |
Narrow the interface used by the processors and memory to the top-level simulator/htif.
This allows the implementation of an alternative top-level simulator class.
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 5f054db..eca8a83 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -4,7 +4,7 @@ #include "sim.h" #include "processor.h" -mmu_t::mmu_t(sim_t* sim, processor_t* proc) +mmu_t::mmu_t(simif_t* sim, processor_t* proc) : sim(sim), proc(proc), check_triggers_fetch(false), check_triggers_load(false), |