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author | Andrew Waterman <andrew@sifive.com> | 2021-07-16 01:15:17 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2021-07-16 01:16:57 -0700 |
commit | 4506ac36121e326f68c3eb9a0c5673a5daa3dc1d (patch) | |
tree | 0791fafcae7437976f4bc88b4205297775643de3 /riscv/mmu.cc | |
parent | 009fc7d7c72b6b15fdb5c9cdca88e2b3119480e3 (diff) | |
download | riscv-isa-sim-4506ac36121e326f68c3eb9a0c5673a5daa3dc1d.zip riscv-isa-sim-4506ac36121e326f68c3eb9a0c5673a5daa3dc1d.tar.gz riscv-isa-sim-4506ac36121e326f68c3eb9a0c5673a5daa3dc1d.tar.bz2 |
Fix MPRV-related bug
The wrong instruction might've been fetched when the PC was on the same
page as a load or store used within the MPRV sequence.
Fix by not using TLB within MPRV sequences.
Resolves #746
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r-- | riscv/mmu.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index a394e63..39c2a15 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -191,6 +191,11 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_ reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES; reg_t expected_tag = vaddr >> PGSHIFT; + tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr}; + + if (proc && get_field(proc->state.mstatus, MSTATUS_MPRV)) + return entry; + if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) tlb_load_tag[idx] = -1; if ((tlb_store_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) @@ -209,7 +214,6 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_ else tlb_load_tag[idx] = expected_tag; } - tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr}; tlb_data[idx] = entry; return entry; } |