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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-18 11:10:56 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-18 11:10:56 -0800 |
| commit | 722b9bf869b7928b060201a794406bcf32a4d532 (patch) | |
| tree | be2cf70460b304ceace00ae0f79f16ccf75e97d8 /riscv/insns/vsaddu_vi.h | |
| parent | 77b98bf87e768eeea7aa1f93cb270843e5cb7b2a (diff) | |
| parent | 4a0ad01f700460a1587581305b8007cc8936663e (diff) | |
| download | riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.zip riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.tar.gz riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.tar.bz2 | |
Merge pull request #396 from chihminchao/rvv-fix-2020-02-14
Rvv fix 2020 02 14
Diffstat (limited to 'riscv/insns/vsaddu_vi.h')
| -rw-r--r-- | riscv/insns/vsaddu_vi.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h index 9d376cc..3f03fd2 100644 --- a/riscv/insns/vsaddu_vi.h +++ b/riscv/insns/vsaddu_vi.h @@ -1,8 +1,8 @@ -// vsaddu vd, vs2, zimm5 +// vsaddu vd, vs2, simm5 VI_VI_ULOOP ({ bool sat = false; - vd = vs2 + simm5; + vd = vs2 + (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); sat = vd < vs2; vd |= -(vd < vs2); |