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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-18 11:10:56 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-18 11:10:56 -0800 |
| commit | 722b9bf869b7928b060201a794406bcf32a4d532 (patch) | |
| tree | be2cf70460b304ceace00ae0f79f16ccf75e97d8 /riscv/insns/vmv_s_x.h | |
| parent | 77b98bf87e768eeea7aa1f93cb270843e5cb7b2a (diff) | |
| parent | 4a0ad01f700460a1587581305b8007cc8936663e (diff) | |
| download | riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.zip riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.tar.gz riscv-isa-sim-722b9bf869b7928b060201a794406bcf32a4d532.tar.bz2 | |
Merge pull request #396 from chihminchao/rvv-fix-2020-02-14
Rvv fix 2020 02 14
Diffstat (limited to 'riscv/insns/vmv_s_x.h')
| -rw-r--r-- | riscv/insns/vmv_s_x.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index 948b5be..99db2a0 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -5,7 +5,7 @@ require(P.VU.vsew == e8 || P.VU.vsew == e16 || P.VU.vsew == e32 || P.VU.vsew == e64); reg_t vl = P.VU.vl; -if (vl > 0) { +if (vl > 0 && P.VU.vstart < vl) { reg_t rd_num = insn.rd(); reg_t sew = P.VU.vsew; @@ -26,3 +26,5 @@ if (vl > 0) { vl = 0; } + +P.VU.vstart = 0; |