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| author | Andrew Waterman <andrew@sifive.com> | 2026-04-29 10:58:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-29 10:58:27 -0700 |
| commit | b21cccdc5f4680d9c13a6bd7d9d00b75aea3cbb5 (patch) | |
| tree | 87c74cdee88663a7d7775799fc0006875a651b4b /riscv/insns/sshlr.h | |
| parent | 632777d37139298f0af1ee8d2a001f3ab0bde98c (diff) | |
| parent | f2aa295a31f6d0de376e807b2dfab5a62418c8dc (diff) | |
| download | riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 riscv-isa-sim-master.zip | |
rvp for rv32/rv64
Diffstat (limited to 'riscv/insns/sshlr.h')
| -rw-r--r-- | riscv/insns/sshlr.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/riscv/insns/sshlr.h b/riscv/insns/sshlr.h new file mode 100644 index 00000000..d36b0052 --- /dev/null +++ b/riscv/insns/sshlr.h @@ -0,0 +1,22 @@ +require_extension('P'); +require_rv32; +sreg_t sshamt = P_FIELD(RS2, 0, 8); +if (sshamt < 0) { + uint64_t shx; + if (sshamt < -32) + shx = 0; + else if (sshamt == -32) + shx = (RS1 >> 31) & 1; + else + shx = ((uint64_t)RS1 << 1) >> (-sshamt); + WRITE_RD((uint32_t)((shx + 1) >> 1)); +} else { + uint64_t shx = (sshamt >= 32) ? ((uint64_t)RS1 << 32) : ((uint64_t)RS1 << sshamt); + if (shx > 0xFFFFFFFFULL) { + P.VU.vxsat->write(1); + WRITE_RD(0xFFFFFFFF); + } else { + WRITE_RD((uint32_t)shx); + } +} + |