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| author | Andrew Waterman <andrew@sifive.com> | 2026-04-29 10:58:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-29 10:58:27 -0700 |
| commit | b21cccdc5f4680d9c13a6bd7d9d00b75aea3cbb5 (patch) | |
| tree | 87c74cdee88663a7d7775799fc0006875a651b4b /riscv/insns/srx.h | |
| parent | 632777d37139298f0af1ee8d2a001f3ab0bde98c (diff) | |
| parent | f2aa295a31f6d0de376e807b2dfab5a62418c8dc (diff) | |
| download | riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 riscv-isa-sim-master.zip | |
rvp for rv32/rv64
Diffstat (limited to 'riscv/insns/srx.h')
| -rw-r--r-- | riscv/insns/srx.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/riscv/insns/srx.h b/riscv/insns/srx.h new file mode 100644 index 00000000..19460c74 --- /dev/null +++ b/riscv/insns/srx.h @@ -0,0 +1,16 @@ +require_extension('P'); +if(xlen == 64){ + int shamt = RS2 & 63; + if(shamt == 0){ + WRITE_RD((uint64_t)RD); + }else{ + WRITE_RD(((uint64_t)RS1 << (64 - shamt)) | ((uint64_t)RD >> shamt)); + } +}else{ + int shamt = (uint32_t)RS2 & 31; + if (shamt == 0) { + WRITE_RD(sext_xlen((uint32_t)RD)); + } else { + WRITE_RD(sext_xlen(((uint32_t)RS1 << (32 - shamt)) | ((uint32_t)RD >> shamt))); + } +} |