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| author | Andrew Waterman <andrew@sifive.com> | 2026-04-29 10:58:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-29 10:58:27 -0700 |
| commit | b21cccdc5f4680d9c13a6bd7d9d00b75aea3cbb5 (patch) | |
| tree | 87c74cdee88663a7d7775799fc0006875a651b4b /riscv/insns/predsumu_ws.h | |
| parent | 632777d37139298f0af1ee8d2a001f3ab0bde98c (diff) | |
| parent | f2aa295a31f6d0de376e807b2dfab5a62418c8dc (diff) | |
| download | riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 riscv-isa-sim-master.zip | |
rvp for rv32/rv64
Diffstat (limited to 'riscv/insns/predsumu_ws.h')
| -rw-r--r-- | riscv/insns/predsumu_ws.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/insns/predsumu_ws.h b/riscv/insns/predsumu_ws.h new file mode 100644 index 00000000..98a3aa91 --- /dev/null +++ b/riscv/insns/predsumu_ws.h @@ -0,0 +1,6 @@ +require_rv64; +reg_t rd_tmp = RS2; \ +P_RS1_LOOP_BASE(32) + P_RS1_UPARAMS(32) + rd_tmp += zext_xlen(p_rs1); +P_RD_LOOP_END() |