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| author | Andrew Waterman <andrew@sifive.com> | 2026-04-29 10:58:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-29 10:58:27 -0700 |
| commit | b21cccdc5f4680d9c13a6bd7d9d00b75aea3cbb5 (patch) | |
| tree | 87c74cdee88663a7d7775799fc0006875a651b4b /riscv/insns/pnclipriu_h.h | |
| parent | 632777d37139298f0af1ee8d2a001f3ab0bde98c (diff) | |
| parent | f2aa295a31f6d0de376e807b2dfab5a62418c8dc (diff) | |
| download | riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 riscv-isa-sim-master.zip | |
rvp for rv32/rv64
Diffstat (limited to 'riscv/insns/pnclipriu_h.h')
| -rw-r--r-- | riscv/insns/pnclipriu_h.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/riscv/insns/pnclipriu_h.h b/riscv/insns/pnclipriu_h.h new file mode 100644 index 00000000..4d2dbd9b --- /dev/null +++ b/riscv/insns/pnclipriu_h.h @@ -0,0 +1,13 @@ +require_rv32; +P_NARROW_RD_RS1_ULOOP(16, 32, { + uint32_t shamt = insn.shamtw(); + uint32_t result; + if (shamt == 0) { + result = p_rs1; + } else { + uint32_t shifted = p_rs1 >> shamt; + uint32_t roundbit = (p_rs1 >> (shamt - 1)) & 1; + result = shifted + roundbit; + } + p_rd = P_USAT_FULL(16, (sreg_t)result); +})
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