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| author | Andrew Waterman <andrew@sifive.com> | 2026-04-29 10:58:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-29 10:58:27 -0700 |
| commit | b21cccdc5f4680d9c13a6bd7d9d00b75aea3cbb5 (patch) | |
| tree | 87c74cdee88663a7d7775799fc0006875a651b4b /riscv/insns/cls.h | |
| parent | 632777d37139298f0af1ee8d2a001f3ab0bde98c (diff) | |
| parent | f2aa295a31f6d0de376e807b2dfab5a62418c8dc (diff) | |
| download | riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 riscv-isa-sim-master.zip | |
rvp for rv32/rv64
Diffstat (limited to 'riscv/insns/cls.h')
| -rw-r--r-- | riscv/insns/cls.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/riscv/insns/cls.h b/riscv/insns/cls.h new file mode 100644 index 00000000..3d80b618 --- /dev/null +++ b/riscv/insns/cls.h @@ -0,0 +1,10 @@ +require_extension('P'); +reg_t x = xlen - 1; +reg_t msb = (RS1 >> (xlen - 1)) & 1; +for (int i = 0; i < xlen - 1; i++) { + if (msb != ((RS1 >> (xlen - i - 2)) & 1)) { + x = i; + break; + } +} +WRITE_RD(sext_xlen(x));
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