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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-04 22:22:32 -1000 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-12-05 10:07:30 -1000 |
| commit | 263af1d153cd7cb684633a4ad631dc45b60464cf (patch) | |
| tree | 771986ec5a7aece970336665353b83bff178f767 /riscv/decode.h | |
| parent | 55c90c6561cad00f6c4ee52286256990f5f93496 (diff) | |
| download | riscv-isa-sim-263af1d153cd7cb684633a4ad631dc45b60464cf.zip riscv-isa-sim-263af1d153cd7cb684633a4ad631dc45b60464cf.tar.gz riscv-isa-sim-263af1d153cd7cb684633a4ad631dc45b60464cf.tar.bz2 | |
Simplify implementation of SFENCE.W.INVAL
For Spike, this instruction merely performs exception checks, just like
SFENCE.INVAL.IR. So, implement it in terms of SFENCE.INVAL.IR.
Diffstat (limited to 'riscv/decode.h')
0 files changed, 0 insertions, 0 deletions